sx.vhd

几个VHDL实现的源程序及其代码

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY sx IS
	PORT(
		sj : IN STD_LOGIC_VECTOR(3 downto 0);
		kz : IN STD_LOGIC;
		d : OUT	STD_LOGIC_VECTOR(6 downto 0));
END sx;
ARCHITECTURE a OF sx IS
SIGNAL nsjh,nsjl : STD_LOGIC_VECTOR(6 downto 0);
BEGIN
with sj select
nsjh <= "0000110" when "1111",
        "0000110" when "1110",
        "0000110" when "1101",
        "0000110" when "1100",
        "0000110" when "1011",
        "0000110" when "1010",
        "0000000" when others;
with sj select
nsjl <= "0111111" when "0000",
        "0000110" when "0001",
        "1011011" when "0010",
        "1001111" when "0011",
        "1100110" when "0100",
        "1101101" when "0101",
        "1111101" when "0110",
        "0000111" when "0111",
        "1111111" when "1000",
        "1101111" when "1001",
        "0111111" when "1010",
        "0000110" when "1011",
        "1011011" when "1100",
        "1001111" when "1101",
        "1100110" when "1110",
        "1101101" when "1111",
        "0000000" when others;
with kz select
d <= nsjl when '0',
     nsjh when '1',
     "0000000" when others;
END a;