📄 bijiaoqi.rpt
字号:
- 1 - C 24 OR2 0 4 1 0 |7485:15|f7485:sub|ALBO (|7485:15|f7485:sub|:87)
- 1 - C 22 OR2 s 4 0 0 1 |7485:15|f7485:sub|~88~1
- 6 - C 24 OR2 s 4 0 0 1 |7485:15|f7485:sub|~88~2
- 3 - C 24 OR2 ! 2 0 0 1 |7485:15|f7485:sub|:90
- 8 - C 24 OR2 s 0 3 0 2 |7485:15|f7485:sub|~102~1
- 2 - C 24 AND2 0 3 1 0 |7485:15|f7485:sub|AEBO (|7485:15|f7485:sub|:108)
- 4 - C 24 OR2 2 2 0 3 |7485:15|f7485:sub|:109
- 2 - C 22 OR2 4 0 0 2 |7485:15|f7485:sub|:111
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:c:\windows\desktop\edaplay\test1\bijiaoqi\bijiaoqi.rpt
bijiaoqi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/ 96( 4%) 0/ 48( 0%) 0/ 48( 0%) 4/16( 25%) 0/16( 0%) 0/16( 0%)
B: 4/ 96( 4%) 0/ 48( 0%) 2/ 48( 4%) 4/16( 25%) 0/16( 0%) 0/16( 0%)
C: 11/ 96( 11%) 0/ 48( 0%) 10/ 48( 20%) 5/16( 31%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 4/24( 16%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:c:\windows\desktop\edaplay\test1\bijiaoqi\bijiaoqi.rpt
bijiaoqi
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
A4 : INPUT;
A5 : INPUT;
A6 : INPUT;
A7 : INPUT;
B0 : INPUT;
B1 : INPUT;
B2 : INPUT;
B3 : INPUT;
B4 : INPUT;
B5 : INPUT;
B6 : INPUT;
B7 : INPUT;
-- Node name is 'lamp1'
-- Equation name is 'lamp1', type is output
lamp1 = _LC1_C24;
-- Node name is 'lamp2'
-- Equation name is 'lamp2', type is output
lamp2 = _LC2_C24;
-- Node name is 'lamp3'
-- Equation name is 'lamp3', type is output
lamp3 = _LC5_C24;
-- Node name is '|7485:1|f7485:sub|:84'
-- Equation name is '_LC1_C13', type is buried
_LC1_C13 = LCELL( _EQ001);
_EQ001 = _LC3_C13
# _LC1_B17 & _LC2_C13;
-- Node name is '|7485:1|f7485:sub|~88~1'
-- Equation name is '_LC3_C13', type is buried
-- synthesized logic cell
_LC3_C13 = LCELL( _EQ002);
_EQ002 = A2 & A3 & !B2
# A2 & !B2 & !B3
# A3 & !B3;
-- Node name is '|7485:1|f7485:sub|~88~2'
-- Equation name is '_LC1_B17', type is buried
-- synthesized logic cell
_LC1_B17 = LCELL( _EQ003);
_EQ003 = A1 & !B1
# A0 & !B0 & !B1
# A0 & A1 & !B0;
-- Node name is '|7485:1|f7485:sub|~109~1'
-- Equation name is '_LC4_B17', type is buried
-- synthesized logic cell
_LC4_B17 = LCELL( _EQ004);
_EQ004 = !A1 & B1
# A1 & !B1
# A0 & !B0
# !A0 & B0;
-- Node name is '|7485:1|f7485:sub|:111'
-- Equation name is '_LC2_C13', type is buried
_LC2_C13 = LCELL( _EQ005);
_EQ005 = A2 & A3 & B2 & B3
# A2 & !A3 & B2 & !B3
# !A2 & A3 & !B2 & B3
# !A2 & !A3 & !B2 & !B3;
-- Node name is '|7485:15|f7485:sub|:108' = '|7485:15|f7485:sub|AEBO'
-- Equation name is '_LC2_C24', type is buried
_LC2_C24 = LCELL( _EQ006);
_EQ006 = _LC2_C13 & !_LC4_B17 & _LC4_C24;
-- Node name is '|7485:15|f7485:sub|:86' = '|7485:15|f7485:sub|AGBO'
-- Equation name is '_LC5_C24', type is buried
_LC5_C24 = LCELL( _EQ007);
_EQ007 = _LC1_C13 & _LC8_C24
# _LC7_C24;
-- Node name is '|7485:15|f7485:sub|:87' = '|7485:15|f7485:sub|ALBO'
-- Equation name is '_LC1_C24', type is buried
_LC1_C24 = LCELL( _EQ008);
_EQ008 = !_LC4_C24 & !_LC7_C24
# !_LC1_C13 & _LC8_C24;
-- Node name is '|7485:15|f7485:sub|:84'
-- Equation name is '_LC7_C24', type is buried
_LC7_C24 = LCELL( _EQ009);
_EQ009 = _LC1_C22
# _LC2_C22 & _LC6_C24;
-- Node name is '|7485:15|f7485:sub|~88~1'
-- Equation name is '_LC1_C22', type is buried
-- synthesized logic cell
_LC1_C22 = LCELL( _EQ010);
_EQ010 = A6 & A7 & !B6
# A6 & !B6 & !B7
# A7 & !B7;
-- Node name is '|7485:15|f7485:sub|~88~2'
-- Equation name is '_LC6_C24', type is buried
-- synthesized logic cell
_LC6_C24 = LCELL( _EQ011);
_EQ011 = A4 & !B4 & !B5
# A4 & A5 & !B4
# A5 & !B5;
-- Node name is '|7485:15|f7485:sub|:90'
-- Equation name is '_LC3_C24', type is buried
!_LC3_C24 = _LC3_C24~NOT;
_LC3_C24~NOT = LCELL( _EQ012);
_EQ012 = A4 & !B4
# !A4 & B4;
-- Node name is '|7485:15|f7485:sub|~102~1'
-- Equation name is '_LC8_C24', type is buried
-- synthesized logic cell
_LC8_C24 = LCELL( _EQ013);
_EQ013 = !_LC2_C13 & _LC4_C24
# _LC4_B17 & _LC4_C24;
-- Node name is '|7485:15|f7485:sub|:109'
-- Equation name is '_LC4_C24', type is buried
_LC4_C24 = LCELL( _EQ014);
_EQ014 = A5 & B5 & _LC2_C22 & _LC3_C24
# !A5 & !B5 & _LC2_C22 & _LC3_C24;
-- Node name is '|7485:15|f7485:sub|:111'
-- Equation name is '_LC2_C22', type is buried
_LC2_C22 = LCELL( _EQ015);
_EQ015 = A6 & A7 & B6 & B7
# A6 & !A7 & B6 & !B7
# !A6 & A7 & !B6 & B7
# !A6 & !A7 & !B6 & !B7;
Project Information c:\windows\desktop\edaplay\test1\bijiaoqi\bijiaoqi.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 10,609K
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