📄 4-16decoder.rpt
字号:
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:c:\windows\desktop\edaplay\digital\test1\4-16decoder\4-16decoder.rpt
4-16decoder
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 8/ 96( 8%) 0/ 48( 0%) 0/ 48( 0%) 3/16( 18%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:c:\windows\desktop\edaplay\digital\test1\4-16decoder\4-16decoder.rpt
4-16decoder
** EQUATIONS **
A : INPUT;
B : INPUT;
C : INPUT;
D : INPUT;
-- Node name is 'LED1'
-- Equation name is 'LED1', type is output
LED1 = !_LC1_C13;
-- Node name is 'LED2'
-- Equation name is 'LED2', type is output
LED2 = !_LC3_C13;
-- Node name is 'LED3'
-- Equation name is 'LED3', type is output
LED3 = !_LC5_C13;
-- Node name is 'LED4'
-- Equation name is 'LED4', type is output
LED4 = !_LC7_C13;
-- Node name is 'LED5'
-- Equation name is 'LED5', type is output
LED5 = !_LC5_C5;
-- Node name is 'LED6'
-- Equation name is 'LED6', type is output
LED6 = !_LC1_C8;
-- Node name is 'LED7'
-- Equation name is 'LED7', type is output
LED7 = !_LC4_C10;
-- Node name is 'LED8'
-- Equation name is 'LED8', type is output
LED8 = !_LC1_C10;
-- Node name is 'LED9'
-- Equation name is 'LED9', type is output
LED9 = !_LC4_C12;
-- Node name is 'LED10'
-- Equation name is 'LED10', type is output
LED10 = !_LC8_C13;
-- Node name is 'LED11'
-- Equation name is 'LED11', type is output
LED11 = !_LC1_C15;
-- Node name is 'LED12'
-- Equation name is 'LED12', type is output
LED12 = !_LC4_C15;
-- Node name is 'LED13'
-- Equation name is 'LED13', type is output
LED13 = !_LC1_C17;
-- Node name is 'LED14'
-- Equation name is 'LED14', type is output
LED14 = !_LC5_C17;
-- Node name is 'LED15'
-- Equation name is 'LED15', type is output
LED15 = !_LC1_C19;
-- Node name is 'LED16'
-- Equation name is 'LED16', type is output
LED16 = !_LC5_C19;
-- Node name is '|74154:1|:32' = '|74154:1|O0N'
-- Equation name is '_LC1_C13', type is buried
!_LC1_C13 = _LC1_C13~NOT;
_LC1_C13~NOT = LCELL( _EQ001);
_EQ001 = !A & !B & !C & !D;
-- Node name is '|74154:1|:31' = '|74154:1|O1N'
-- Equation name is '_LC3_C13', type is buried
!_LC3_C13 = _LC3_C13~NOT;
_LC3_C13~NOT = LCELL( _EQ002);
_EQ002 = A & !B & !C & !D;
-- Node name is '|74154:1|:30' = '|74154:1|O2N'
-- Equation name is '_LC5_C13', type is buried
!_LC5_C13 = _LC5_C13~NOT;
_LC5_C13~NOT = LCELL( _EQ003);
_EQ003 = !A & B & !C & !D;
-- Node name is '|74154:1|:29' = '|74154:1|O3N'
-- Equation name is '_LC7_C13', type is buried
!_LC7_C13 = _LC7_C13~NOT;
_LC7_C13~NOT = LCELL( _EQ004);
_EQ004 = A & B & !C & !D;
-- Node name is '|74154:1|:28' = '|74154:1|O4N'
-- Equation name is '_LC5_C5', type is buried
!_LC5_C5 = _LC5_C5~NOT;
_LC5_C5~NOT = LCELL( _EQ005);
_EQ005 = !A & !B & C & !D;
-- Node name is '|74154:1|:27' = '|74154:1|O5N'
-- Equation name is '_LC1_C8', type is buried
!_LC1_C8 = _LC1_C8~NOT;
_LC1_C8~NOT = LCELL( _EQ006);
_EQ006 = A & !B & C & !D;
-- Node name is '|74154:1|:26' = '|74154:1|O6N'
-- Equation name is '_LC4_C10', type is buried
!_LC4_C10 = _LC4_C10~NOT;
_LC4_C10~NOT = LCELL( _EQ007);
_EQ007 = !A & B & C & !D;
-- Node name is '|74154:1|:25' = '|74154:1|O7N'
-- Equation name is '_LC1_C10', type is buried
!_LC1_C10 = _LC1_C10~NOT;
_LC1_C10~NOT = LCELL( _EQ008);
_EQ008 = A & B & C & !D;
-- Node name is '|74154:1|:24' = '|74154:1|O8N'
-- Equation name is '_LC4_C12', type is buried
!_LC4_C12 = _LC4_C12~NOT;
_LC4_C12~NOT = LCELL( _EQ009);
_EQ009 = !A & !B & !C & D;
-- Node name is '|74154:1|:23' = '|74154:1|O9N'
-- Equation name is '_LC8_C13', type is buried
!_LC8_C13 = _LC8_C13~NOT;
_LC8_C13~NOT = LCELL( _EQ010);
_EQ010 = A & !B & !C & D;
-- Node name is '|74154:1|:22' = '|74154:1|O10N'
-- Equation name is '_LC1_C15', type is buried
!_LC1_C15 = _LC1_C15~NOT;
_LC1_C15~NOT = LCELL( _EQ011);
_EQ011 = !A & B & !C & D;
-- Node name is '|74154:1|:21' = '|74154:1|O11N'
-- Equation name is '_LC4_C15', type is buried
!_LC4_C15 = _LC4_C15~NOT;
_LC4_C15~NOT = LCELL( _EQ012);
_EQ012 = A & B & !C & D;
-- Node name is '|74154:1|:20' = '|74154:1|O12N'
-- Equation name is '_LC1_C17', type is buried
!_LC1_C17 = _LC1_C17~NOT;
_LC1_C17~NOT = LCELL( _EQ013);
_EQ013 = !A & !B & C & D;
-- Node name is '|74154:1|:19' = '|74154:1|O13N'
-- Equation name is '_LC5_C17', type is buried
!_LC5_C17 = _LC5_C17~NOT;
_LC5_C17~NOT = LCELL( _EQ014);
_EQ014 = A & !B & C & D;
-- Node name is '|74154:1|:18' = '|74154:1|O14N'
-- Equation name is '_LC1_C19', type is buried
!_LC1_C19 = _LC1_C19~NOT;
_LC1_C19~NOT = LCELL( _EQ015);
_EQ015 = !A & B & C & D;
-- Node name is '|74154:1|:17' = '|74154:1|O15N'
-- Equation name is '_LC5_C19', type is buried
!_LC5_C19 = _LC5_C19~NOT;
_LC5_C19~NOT = LCELL( _EQ016);
_EQ016 = A & B & C & D;
Project Informationc:\windows\desktop\edaplay\digital\test1\4-16decoder\4-16decoder.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,721K
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