📄 encode.rpt
字号:
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 06 OR2 1 1 1 0 :420
- 1 - C 11 OR2 ! 4 0 0 3 :422
- 4 - C 11 OR2 4 0 0 1 :444
- 3 - C 11 OR2 3 1 1 0 :453
- 6 - C 11 OR2 3 0 0 1 :476
- 7 - C 11 OR2 2 1 0 1 :482
- 5 - C 11 OR2 3 1 1 0 :486
- 7 - C 06 OR2 2 2 1 0 :519
- 2 - C 11 OR2 s ! 3 0 0 2 ~521~1
- 8 - C 06 OR2 2 2 1 0 :552
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:c:\windows\desktop\edaplay\digital\test1\encode\encode.rpt
encode
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 2/ 96( 2%) 0/ 48( 0%) 0/ 48( 0%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
C: 10/ 96( 10%) 5/ 48( 10%) 0/ 48( 0%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:c:\windows\desktop\edaplay\digital\test1\encode\encode.rpt
encode
** EQUATIONS **
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
d4 : INPUT;
d5 : INPUT;
d6 : INPUT;
d7 : INPUT;
ein : INPUT;
-- Node name is 'a0n'
-- Equation name is 'a0n', type is output
a0n = _LC5_C11;
-- Node name is 'a1n'
-- Equation name is 'a1n', type is output
a1n = _LC3_C11;
-- Node name is 'a2n'
-- Equation name is 'a2n', type is output
a2n = _LC1_C6;
-- Node name is 'eon'
-- Equation name is 'eon', type is output
eon = _LC8_C6;
-- Node name is 'gsn'
-- Equation name is 'gsn', type is output
gsn = _LC7_C6;
-- Node name is ':420'
-- Equation name is '_LC1_C6', type is buried
_LC1_C6 = LCELL( _EQ001);
_EQ001 = ein
# _LC1_C11;
-- Node name is ':422'
-- Equation name is '_LC1_C11', type is buried
!_LC1_C11 = _LC1_C11~NOT;
_LC1_C11~NOT = LCELL( _EQ002);
_EQ002 = !d4
# !d5
# !d6
# !d7;
-- Node name is ':444'
-- Equation name is '_LC4_C11', type is buried
_LC4_C11 = LCELL( _EQ003);
_EQ003 = !d4
# !d5
# d2 & d3;
-- Node name is ':453'
-- Equation name is '_LC3_C11', type is buried
_LC3_C11 = LCELL( _EQ004);
_EQ004 = d6 & d7 & _LC4_C11
# ein;
-- Node name is ':476'
-- Equation name is '_LC6_C11', type is buried
_LC6_C11 = LCELL( _EQ005);
_EQ005 = d1 & d3
# !d2 & d3;
-- Node name is ':482'
-- Equation name is '_LC7_C11', type is buried
_LC7_C11 = LCELL( _EQ006);
_EQ006 = d5 & _LC6_C11
# !d4 & d5;
-- Node name is ':486'
-- Equation name is '_LC5_C11', type is buried
_LC5_C11 = LCELL( _EQ007);
_EQ007 = d7 & _LC7_C11
# !d6 & d7
# ein;
-- Node name is ':519'
-- Equation name is '_LC7_C6', type is buried
_LC7_C6 = LCELL( _EQ008);
_EQ008 = d1 & _LC1_C11 & _LC2_C11
# ein;
-- Node name is '~521~1'
-- Equation name is '~521~1', location is LC2_C11, type is buried.
-- synthesized logic cell
!_LC2_C11 = _LC2_C11~NOT;
_LC2_C11~NOT = LCELL( _EQ009);
_EQ009 = !d2
# !d3
# !d0;
-- Node name is ':552'
-- Equation name is '_LC8_C6', type is buried
_LC8_C6 = LCELL( _EQ010);
_EQ010 = ein
# !_LC1_C11
# !d1
# !_LC2_C11;
Project Information c:\windows\desktop\edaplay\digital\test1\encode\encode.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,878K
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