📄 adc.rpt
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** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 04 DFFE 2 0 1 0 |AD:18|QQQ7 (|AD:18|:23)
- 1 - A 01 DFFE 2 0 1 0 |AD:18|QQQ6 (|AD:18|:24)
- 2 - A 01 DFFE 2 0 1 0 |AD:18|QQQ5 (|AD:18|:25)
- 4 - A 01 DFFE 2 0 1 0 |AD:18|QQQ4 (|AD:18|:26)
- 4 - A 04 DFFE 2 0 1 0 |AD:18|QQQ3 (|AD:18|:27)
- 6 - A 04 DFFE 2 0 1 0 |AD:18|QQQ2 (|AD:18|:28)
- 2 - A 04 DFFE 2 0 1 0 |AD:18|QQQ1 (|AD:18|:29)
- 2 - B 05 DFFE 2 0 1 0 |AD:18|QQQ0 (|AD:18|:30)
- 1 - B 16 DFFE +s 1 0 1 0 |AD:18|DK~1 (|AD:18|~32~1)
- 4 - B 18 DFFE + 1 0 1 0 |AD:18|DK (|AD:18|:32)
- 4 - A 20 LCELL s 1 0 1 0 OE~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\windows\desktop\edaplay\digital\test15\adc.rpt
adc
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 8/ 96( 8%) 1/ 48( 2%) 0/ 48( 0%) 4/16( 25%) 1/16( 6%) 0/16( 0%)
B: 3/ 96( 3%) 0/ 48( 0%) 0/ 48( 0%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\windows\desktop\edaplay\digital\test15\adc.rpt
adc
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 11 EOC
INPUT 2 ST
Device-Specific Information: c:\windows\desktop\edaplay\digital\test15\adc.rpt
adc
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 11 EOC
Device-Specific Information: c:\windows\desktop\edaplay\digital\test15\adc.rpt
adc
** EQUATIONS **
D0 : INPUT;
D1 : INPUT;
D2 : INPUT;
D3 : INPUT;
D4 : INPUT;
D5 : INPUT;
D6 : INPUT;
D7 : INPUT;
EOC : INPUT;
ST : INPUT;
-- Node name is 'ADDA'
-- Equation name is 'ADDA', type is output
ADDA = VCC;
-- Node name is 'ALE'
-- Equation name is 'ALE', type is output
ALE = _LC4_B18;
-- Node name is 'OE'
-- Equation name is 'OE', type is output
OE = !_LC4_A20;
-- Node name is 'OE~1'
-- Equation name is 'OE~1', location is LC4_A20, type is buried.
-- synthesized logic cell
_LC4_A20 = LCELL( EOC);
-- Node name is 'qq0'
-- Equation name is 'qq0', type is output
qq0 = _LC2_B5;
-- Node name is 'qq1'
-- Equation name is 'qq1', type is output
qq1 = _LC2_A4;
-- Node name is 'qq2'
-- Equation name is 'qq2', type is output
qq2 = _LC6_A4;
-- Node name is 'qq3'
-- Equation name is 'qq3', type is output
qq3 = _LC4_A4;
-- Node name is 'qq4'
-- Equation name is 'qq4', type is output
qq4 = _LC4_A1;
-- Node name is 'qq5'
-- Equation name is 'qq5', type is output
qq5 = _LC2_A1;
-- Node name is 'qq6'
-- Equation name is 'qq6', type is output
qq6 = _LC1_A1;
-- Node name is 'qq7'
-- Equation name is 'qq7', type is output
qq7 = _LC1_A4;
-- Node name is 'STA'
-- Equation name is 'STA', type is output
STA = _LC1_B16;
-- Node name is '|AD:18|:32' = '|AD:18|DK'
-- Equation name is '_LC4_B18', type is buried
_LC4_B18 = DFFE( VCC, GLOBAL( ST), EOC, VCC, VCC);
-- Node name is '|AD:18|~32~1' = '|AD:18|DK~1'
-- Equation name is '_LC1_B16', type is buried
-- synthesized logic cell
_LC1_B16 = DFFE( VCC, GLOBAL( ST), EOC, VCC, VCC);
-- Node name is '|AD:18|:30' = '|AD:18|QQQ0'
-- Equation name is '_LC2_B5', type is buried
_LC2_B5 = DFFE( D0, EOC, VCC, VCC, VCC);
-- Node name is '|AD:18|:29' = '|AD:18|QQQ1'
-- Equation name is '_LC2_A4', type is buried
_LC2_A4 = DFFE( D1, EOC, VCC, VCC, VCC);
-- Node name is '|AD:18|:28' = '|AD:18|QQQ2'
-- Equation name is '_LC6_A4', type is buried
_LC6_A4 = DFFE( D2, EOC, VCC, VCC, VCC);
-- Node name is '|AD:18|:27' = '|AD:18|QQQ3'
-- Equation name is '_LC4_A4', type is buried
_LC4_A4 = DFFE( D3, EOC, VCC, VCC, VCC);
-- Node name is '|AD:18|:26' = '|AD:18|QQQ4'
-- Equation name is '_LC4_A1', type is buried
_LC4_A1 = DFFE( D4, EOC, VCC, VCC, VCC);
-- Node name is '|AD:18|:25' = '|AD:18|QQQ5'
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = DFFE( D5, EOC, VCC, VCC, VCC);
-- Node name is '|AD:18|:24' = '|AD:18|QQQ6'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = DFFE( D6, EOC, VCC, VCC, VCC);
-- Node name is '|AD:18|:23' = '|AD:18|QQQ7'
-- Equation name is '_LC1_A4', type is buried
_LC1_A4 = DFFE( D7, EOC, VCC, VCC, VCC);
Project Information c:\windows\desktop\edaplay\digital\test15\adc.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:03
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:01
Fitter 00:00:04
Timing SNF Extractor 00:00:01
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:11
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,454K
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