📄 ad.rpt
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Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\windows\desktop\edaplay\test15\ad.rpt
ad
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 1/ 48( 2%) 2/ 48( 4%) 1/16( 6%) 4/16( 25%) 0/16( 0%)
B: 1/ 96( 1%) 2/ 48( 4%) 1/ 48( 2%) 1/16( 6%) 4/16( 25%) 0/16( 0%)
C: 2/ 96( 2%) 1/ 48( 2%) 3/ 48( 6%) 2/16( 12%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\windows\desktop\edaplay\test15\ad.rpt
ad
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 11 EOC
INPUT 2 ST
Device-Specific Information: c:\windows\desktop\edaplay\test15\ad.rpt
ad
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 11 EOC
Device-Specific Information: c:\windows\desktop\edaplay\test15\ad.rpt
ad
** EQUATIONS **
DD0 : INPUT;
DD1 : INPUT;
DD2 : INPUT;
DD3 : INPUT;
DD4 : INPUT;
DD5 : INPUT;
DD6 : INPUT;
DD7 : INPUT;
EOC : INPUT;
ST : INPUT;
-- Node name is 'ADDA'
-- Equation name is 'ADDA', type is output
ADDA = VCC;
-- Node name is 'ALE'
-- Equation name is 'ALE', type is output
ALE = _LC1_C17;
-- Node name is ':32' = 'DK'
-- Equation name is 'DK', location is LC4_C17, type is buried.
DK = DFFE( VCC, GLOBAL( ST), EOC, VCC, VCC);
-- Node name is '~32~1' = 'DK~1'
-- Equation name is '~32~1', location is LC1_C17, type is buried.
-- synthesized logic cell
_LC1_C17 = DFFE( VCC, GLOBAL( ST), EOC, VCC, VCC);
-- Node name is 'OE'
-- Equation name is 'OE', type is output
OE = !_LC6_B1;
-- Node name is 'OE~1'
-- Equation name is 'OE~1', location is LC6_B1, type is buried.
-- synthesized logic cell
_LC6_B1 = LCELL( EOC);
-- Node name is ':30' = 'QQQ0'
-- Equation name is 'QQQ0', location is LC1_A3, type is buried.
QQQ0 = DFFE( DD0, GLOBAL( EOC), VCC, VCC, VCC);
-- Node name is ':29' = 'QQQ1'
-- Equation name is 'QQQ1', location is LC1_B5, type is buried.
QQQ1 = DFFE( DD1, GLOBAL( EOC), VCC, VCC, VCC);
-- Node name is ':28' = 'QQQ2'
-- Equation name is 'QQQ2', location is LC3_A15, type is buried.
QQQ2 = DFFE( DD2, GLOBAL( EOC), VCC, VCC, VCC);
-- Node name is ':27' = 'QQQ3'
-- Equation name is 'QQQ3', location is LC8_A22, type is buried.
QQQ3 = DFFE( DD3, GLOBAL( EOC), VCC, VCC, VCC);
-- Node name is ':26' = 'QQQ4'
-- Equation name is 'QQQ4', location is LC1_A14, type is buried.
QQQ4 = DFFE( DD4, GLOBAL( EOC), VCC, VCC, VCC);
-- Node name is ':25' = 'QQQ5'
-- Equation name is 'QQQ5', location is LC7_C16, type is buried.
QQQ5 = DFFE( DD5, GLOBAL( EOC), VCC, VCC, VCC);
-- Node name is ':24' = 'QQQ6'
-- Equation name is 'QQQ6', location is LC1_B17, type is buried.
QQQ6 = DFFE( DD6, GLOBAL( EOC), VCC, VCC, VCC);
-- Node name is ':23' = 'QQQ7'
-- Equation name is 'QQQ7', location is LC8_C4, type is buried.
QQQ7 = DFFE( DD7, GLOBAL( EOC), VCC, VCC, VCC);
-- Node name is 'QQ0'
-- Equation name is 'QQ0', type is output
QQ0 = QQQ0;
-- Node name is 'QQ1'
-- Equation name is 'QQ1', type is output
QQ1 = QQQ1;
-- Node name is 'QQ2'
-- Equation name is 'QQ2', type is output
QQ2 = QQQ2;
-- Node name is 'QQ3'
-- Equation name is 'QQ3', type is output
QQ3 = QQQ3;
-- Node name is 'QQ4'
-- Equation name is 'QQ4', type is output
QQ4 = QQQ4;
-- Node name is 'QQ5'
-- Equation name is 'QQ5', type is output
QQ5 = QQQ5;
-- Node name is 'QQ6'
-- Equation name is 'QQ6', type is output
QQ6 = QQQ6;
-- Node name is 'QQ7'
-- Equation name is 'QQ7', type is output
QQ7 = QQQ7;
-- Node name is 'STA'
-- Equation name is 'STA', type is output
STA = DK;
Project Information c:\windows\desktop\edaplay\test15\ad.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 9,832K
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