📄 time.rpt
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** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 12 DFFE + 0 2 1 2 |alert:34|lamp0~
- 2 - A 12 DFFE + 0 3 1 2 |alert:34|lamp1~
- 5 - A 12 DFFE + 0 3 1 1 |alert:34|lamp2~
- 2 - A 11 DFFE 0 2 0 1 |alert:34|s
- 8 - A 12 AND2 s 0 4 0 1 |alert:34|~58~1
- 7 - A 12 AND2 ! 0 4 0 6 |alert:34|:58
- 1 - A 11 AND2 1 1 0 1 |alert:34|:60
- 4 - A 17 AND2 ! 0 4 0 1 |deled:62|:41
- 3 - A 16 AND2 s 0 2 0 1 |deled:62|~59~1
- 1 - A 17 OR2 s 0 4 0 2 |deled:62|~228~1
- 8 - A 17 OR2 s 0 4 0 1 |deled:62|~228~2
- 5 - A 17 OR2 0 3 1 0 |deled:62|:228
- 7 - A 17 OR2 0 4 1 0 |deled:62|:230
- 7 - A 16 OR2 s 0 4 0 1 |deled:62|~246~1
- 4 - A 16 OR2 0 3 1 0 |deled:62|:246
- 6 - A 16 OR2 s 0 4 0 2 |deled:62|~261~1
- 8 - A 16 OR2 s 0 4 0 1 |deled:62|~261~2
- 2 - A 16 OR2 0 3 1 0 |deled:62|:261
- 6 - A 17 OR2 s 0 4 0 1 |deled:62|~263~1
- 1 - A 22 OR2 s 0 4 0 1 |deled:62|~263~2
- 2 - A 17 OR2 0 4 1 0 |deled:62|:263
- 3 - A 22 OR2 s 0 4 0 1 |deled:62|~265~1
- 4 - A 22 OR2 0 3 1 0 |deled:62|:265
- 1 - A 16 OR2 s 0 4 0 2 |deled:62|~267~1
- 5 - A 16 OR2 s 0 4 0 2 |deled:62|~267~2
- 3 - A 17 OR2 s 0 4 0 1 |deled:62|~267~3
- 2 - A 22 OR2 s 0 4 0 1 |deled:62|~267~4
- 6 - A 22 OR2 0 4 1 0 |deled:62|:267
- 2 - A 05 DFFE 1 1 0 4 |hour:31|count0
- 4 - A 05 DFFE 1 3 0 3 |hour:31|count1
- 2 - A 07 DFFE 1 3 0 5 |hour:31|count2
- 1 - A 07 DFFE 1 4 0 4 |hour:31|count3
- 3 - A 07 DFFE 1 4 0 4 |hour:31|count4
- 4 - A 07 DFFE 1 4 0 3 |hour:31|count5
- 8 - A 05 AND2 ! 0 4 0 3 |hour:31|:45
- 6 - A 07 OR2 s 0 3 0 1 |hour:31|~90~1
- 5 - A 07 OR2 0 4 0 5 |hour:31|:91
- 5 - A 05 OR2 ! 0 2 0 4 |hour:31|:98
- 7 - A 07 AND2 0 3 0 2 |hour:31|:106
- 8 - A 07 OR2 0 4 0 1 |hour:31|:125
- 4 - A 02 DFFE 1 2 0 6 |minute:32|count0
- 3 - A 12 DFFE 1 3 0 5 |minute:32|count1
- 6 - A 12 DFFE 1 4 0 4 |minute:32|count2
- 1 - A 10 DFFE 1 3 0 6 |minute:32|count3
- 3 - A 10 DFFE 1 4 0 7 |minute:32|count4
- 4 - A 10 DFFE 1 4 0 6 |minute:32|count5
- 2 - A 10 DFFE 1 4 0 5 |minute:32|count6
- 5 - A 10 DFFE 1 5 0 1 |minute:32|s
- 2 - A 21 DFFE + ! 2 0 0 1 |minute:32|sh
- 1 - A 21 OR2 0 2 0 6 |minute:32|:51
- 4 - A 12 AND2 ! 0 4 0 10 |minute:32|:56
- 8 - A 10 OR2 0 4 0 1 |minute:32|:103
- 6 - A 10 OR2 0 4 0 1 |minute:32|:104
- 1 - A 02 AND2 0 3 0 4 |minute:32|:118
- 1 - A 09 AND2 0 3 0 1 |minute:32|:126
- 7 - A 10 AND2 0 4 0 1 |minute:32|:130
- 5 - A 06 DFFE + 1 0 0 5 |minute:78|count0
- 2 - A 03 DFFE + 1 2 0 4 |minute:78|count1
- 5 - A 03 DFFE + 1 3 0 3 |minute:78|count2
- 3 - A 02 DFFE + 1 2 0 5 |minute:78|count3
- 5 - A 02 DFFE + 1 3 0 6 |minute:78|count4
- 5 - A 08 DFFE + 1 3 0 5 |minute:78|count5
- 2 - A 08 DFFE + 1 3 0 4 |minute:78|count6
- 6 - A 08 DFFE + 1 4 0 1 |minute:78|s
- 8 - A 08 DFFE + ! 2 0 0 1 |minute:78|sh
- 7 - A 08 OR2 0 2 0 8 |minute:78|:51
- 8 - A 03 OR2 0 4 0 9 |minute:78|:56
- 4 - A 08 OR2 0 4 0 1 |minute:78|:103
- 1 - A 08 OR2 0 4 0 1 |minute:78|:104
- 4 - A 03 AND2 0 3 0 4 |minute:78|:118
- 6 - A 02 AND2 0 3 0 1 |minute:78|:126
- 3 - A 08 AND2 0 4 0 1 |minute:78|:130
- 2 - A 06 DFFE + 1 2 0 12 |seltime:35|count0
- 3 - A 06 DFFE + 1 2 0 12 |seltime:35|count1
- 6 - A 06 DFFE + 1 2 0 12 |seltime:35|count2
- 7 - A 06 AND2 ! 0 3 1 4 |seltime:35|:81
- 2 - A 04 AND2 ! 0 3 1 3 |seltime:35|:92
- 8 - A 04 AND2 ! 0 3 1 4 |seltime:35|:105
- 5 - A 04 AND2 ! 0 3 1 3 |seltime:35|:122
- 7 - A 01 AND2 ! 0 3 1 4 |seltime:35|:135
- 7 - A 03 OR2 s 0 4 0 1 |seltime:35|~145~1
- 6 - A 03 OR2 s 0 3 0 1 |seltime:35|~145~2
- 6 - A 04 OR2 s 0 3 0 1 |seltime:35|~145~3
- 1 - A 05 OR2 0 3 0 15 |seltime:35|:145
- 7 - A 02 OR2 s 0 4 0 1 |seltime:35|~148~1
- 2 - A 02 OR2 0 3 0 15 |seltime:35|:148
- 3 - A 04 OR2 0 4 0 1 |seltime:35|:149
- 3 - A 03 OR2 s 0 4 0 1 |seltime:35|~150~1
- 4 - A 04 OR2 s 0 3 0 1 |seltime:35|~150~2
- 7 - A 04 OR2 s 0 3 0 1 |seltime:35|~150~3
- 1 - A 04 OR2 0 4 0 15 |seltime:35|:150
- 4 - A 06 OR2 ! 0 4 0 1 |seltime:35|:151
- 1 - A 03 OR2 s ! 0 4 0 1 |seltime:35|~152~1
- 6 - A 05 OR2 s ! 0 3 0 1 |seltime:35|~152~2
- 7 - A 05 OR2 s ! 0 3 0 1 |seltime:35|~152~3
- 3 - A 05 OR2 ! 0 4 0 15 |seltime:35|:152
- 8 - A 11 AND2 1 2 1 0 :75
- 1 - A 01 AND2 ! 0 3 1 0 |74138:51|Y5N (|74138:51|:20)
- 3 - A 01 AND2 ! 0 3 1 0 |74138:51|Y6N (|74138:51|:21)
- 1 - A 06 AND2 ! 0 3 1 0 |74138:51|Y7N (|74138:51|:22)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:c:\windows\desktop\alteraprogramm\digital\test9\time.rpt
time
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 23/ 96( 23%) 33/ 48( 68%) 2/ 48( 4%) 1/16( 6%) 4/16( 25%) 0/16( 0%)
B: 4/ 96( 4%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 1/ 96( 1%) 3/ 48( 6%) 0/ 48( 0%) 1/16( 6%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:c:\windows\desktop\alteraprogramm\digital\test9\time.rpt
time
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 12 CLK
LCELL 8 |minute:78|:51
LCELL 6 |minute:32|:51
INPUT 5 CKDSP
LCELL 1 |alert:34|:60
Device-Specific Information:c:\windows\desktop\alteraprogramm\digital\test9\time.rpt
time
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 27 RESET
Device-Specific Information:c:\windows\desktop\alteraprogramm\digital\test9\time.rpt
time
** EQUATIONS **
CKDSP : INPUT;
CLK : INPUT;
RESET : INPUT;
SETHOUR : INPUT;
SETMIN : INPUT;
spclk : INPUT;
-- Node name is 'A'
-- Equation name is 'A', type is output
A = _LC2_A16;
-- Node name is 'B'
-- Equation name is 'B', type is output
B = _LC5_A17;
-- Node name is 'C'
-- Equation name is 'C', type is output
C = _LC7_A17;
-- Node name is 'D'
-- Equation name is 'D', type is output
D = _LC4_A16;
-- Node name is 'E'
-- Equation name is 'E', type is output
E = _LC2_A17;
-- Node name is 'F'
-- Equation name is 'F', type is output
F = _LC4_A22;
-- Node name is 'G'
-- Equation name is 'G', type is output
G = _LC6_A22;
-- Node name is 'h'
-- Equation name is 'h', type is output
h = GND;
-- Node name is 'LAMP0'
-- Equation name is 'LAMP0', type is output
LAMP0 = _LC1_A12;
-- Node name is 'LAMP1'
-- Equation name is 'LAMP1', type is output
LAMP1 = _LC2_A12;
-- Node name is 'LAMP2'
-- Equation name is 'LAMP2', type is output
LAMP2 = _LC5_A12;
-- Node name is 'SPEAK'
-- Equation name is 'SPEAK', type is output
SPEAK = _LC8_A11;
-- Node name is 'y0'
-- Equation name is 'y0', type is output
y0 = !_LC7_A6;
-- Node name is 'y1'
-- Equation name is 'y1', type is output
y1 = !_LC2_A4;
-- Node name is 'y2'
-- Equation name is 'y2', type is output
y2 = !_LC8_A4;
-- Node name is 'y3'
-- Equation name is 'y3', type is output
y3 = !_LC5_A4;
-- Node name is 'y4'
-- Equation name is 'y4', type is output
y4 = !_LC7_A1;
-- Node name is 'y5'
-- Equation name is 'y5', type is output
y5 = !_LC1_A1;
-- Node name is 'y6'
-- Equation name is 'y6', type is output
y6 = !_LC3_A1;
-- Node name is 'y7'
-- Equation name is 'y7', type is output
y7 = !_LC1_A6;
-- Node name is '|alert:34|lamp0~' from file "alert.tdf" line 9, column 29
-- Equation name is '_LC1_A12', type is buried
_LC1_A12 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = !_LC1_A12 & !_LC2_A12 & !_LC7_A12;
-- Node name is '|alert:34|lamp1~' from file "alert.tdf" line 9, column 29
-- Equation name is '_LC2_A12', type is buried
_LC2_A12 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = _LC1_A12 & !_LC2_A12 & !_LC5_A12 & !_LC7_A12;
-- Node name is '|alert:34|lamp2~' from file "alert.tdf" line 9, column 29
-- Equation name is '_LC5_A12', type is buried
_LC5_A12 = DFFE( _EQ003, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = !_LC1_A12 & _LC2_A12 & !_LC5_A12 & !_LC7_A12;
-- Node name is '|alert:34|s' from file "alert.tdf" line 8, column 4
-- Equation name is '_LC2_A11', type is buried
_LC2_A11 = DFFE( _EQ004, _LC1_A11, VCC, VCC, VCC);
_EQ004 = !_LC2_A11 & !_LC7_A12;
-- Node name is '|alert:34|~58~1' from file "alert.tdf" line 18, column 13
-- Equation name is '_LC8_A12', type is buried
-- synthesized logic cell
_LC8_A12 = LCELL( _EQ005);
_EQ005 = !_LC1_A10 & !_LC2_A10 & !_LC3_A12 & !_LC6_A12;
-- Node name is '|alert:34|:58' from file "alert.tdf" line 18, column 13
-- Equation name is '_LC7_A12', type is buried
!_LC7_A12 = _LC7_A12~NOT;
_LC7_A12~NOT = LCELL( _EQ006);
_EQ006 = !_LC3_A10 & !_LC4_A2 & !_LC4_A10 & _LC8_A12;
-- Node name is '|alert:34|:60' from file "alert.tdf" line 19, column 12
-- Equation name is '_LC1_A11', type is buried
_LC1_A11 = LCELL( _EQ007);
_EQ007 = CLK & !_LC7_A12;
-- Node name is '|deled:62|:41' from file "deled.tdf" line 10, column 5
-- Equation name is '_LC4_A17', type is buried
!_LC4_A17 = _LC4_A17~NOT;
_LC4_A17~NOT = LCELL( _EQ008);
_EQ008 = !_LC1_A4 & !_LC1_A5 & !_LC2_A2 & !_LC3_A5;
-- Node name is '|deled:62|~59~1' from file "deled.tdf" line 12, column 5
-- Equation name is '_LC3_A16', type is buried
-- synthesized logic cell
_LC3_A16 = LCELL( _EQ009);
_EQ009 = !_LC1_A4 & _LC3_A5;
-- Node name is '|deled:62|~228~1' from file "deled.tdf" line 23, column 20
-- Equation name is '_LC1_A17', type is buried
-- synthesized logic cell
_LC1_A17 = LCELL( _EQ010);
_EQ010 = _LC1_A4 & _LC1_A5 & !_LC2_A2 & _LC3_A5
# !_LC1_A4 & _LC1_A5 & !_LC2_A2 & !_LC3_A5
# _LC1_A4 & !_LC1_A5 & !_LC2_A2 & !_LC3_A5;
-- Node name is '|deled:62|~228~2' from file "deled.tdf" line 23, column 20
-- Equation name is '_LC8_A17', type is buried
-- synthesized logic cell
_LC8_A17 = LCELL( _EQ011);
_EQ011 = !_LC1_A5 & _LC2_A2 & !_LC3_A5
# _LC1_A4 & !_LC1_A5 & !_LC2_A2 & _LC3_A5;
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