color.rpt

几个VHDL实现的源程序及其代码

-- Node name is ':871' 
-- Equation name is '_LC1_C11', type is buried 
!_LC1_C11 = _LC1_C11~NOT;
_LC1_C11~NOT = LCELL( _EQ032);
  _EQ032 = !_LC1_C2
         # !ll7
         # !ll8;

-- Node name is ':1098' 
-- Equation name is '_LC5_A13', type is buried 
_LC5_A13 = LCELL( _EQ033);
  _EQ033 = !cc2 & !cc3 & !cc4 & !_LC2_A16;

-- Node name is ':1125' 
-- Equation name is '_LC6_A23', type is buried 
!_LC6_A23 = _LC6_A23~NOT;
_LC6_A23~NOT = LCELL( _EQ034);
  _EQ034 =  cc4
         #  cc3
         #  cc1 &  cc2;

-- Node name is ':1152' 
-- Equation name is '_LC5_A23', type is buried 
_LC5_A23 = LCELL( _EQ035);
  _EQ035 = !cc2 & !cc4 &  _LC5_A16
         # !cc3 & !cc4;

-- Node name is ':1182' 
-- Equation name is '_LC1_A13', type is buried 
_LC1_A13 = LCELL( _EQ036);
  _EQ036 = !cc3
         # !cc2;

-- Node name is ':1231' 
-- Equation name is '_LC7_A23', type is buried 
!_LC7_A23 = _LC7_A23~NOT;
_LC7_A23~NOT = LCELL( _EQ037);
  _EQ037 =  cc1 &  cc4
         #  cc2 &  cc4
         #  cc3 &  cc4;

-- Node name is ':1270' 
-- Equation name is '_LC5_A16', type is buried 
_LC5_A16 = LCELL( _EQ038);
  _EQ038 = !cc0 & !cc1;

-- Node name is ':1373' 
-- Equation name is '_LC3_A23', type is buried 
_LC3_A23 = LCELL( _EQ039);
  _EQ039 = !_LC8_A23
         #  _LC5_A13
         #  _LC6_A23;

-- Node name is '~1396~1' 
-- Equation name is '~1396~1', location is LC8_A23, type is buried.
-- synthesized logic cell 
!_LC8_A23 = _LC8_A23~NOT;
_LC8_A23~NOT = LCELL( _EQ040);
  _EQ040 = !cc3 & !cc4
         # !cc2 & !cc4
         #  _LC5_A23;

-- Node name is ':1397' 
-- Equation name is '_LC2_A23', type is buried 
_LC2_A23 = LCELL( _EQ041);
  _EQ041 =  _LC7_A23 &  _LC8_A23
         #  _LC5_A13
         #  _LC6_A23;

-- Node name is '~1421~1' 
-- Equation name is '~1421~1', location is LC1_A23, type is buried.
-- synthesized logic cell 
_LC1_A23 = LCELL( _EQ042);
  _EQ042 = !cc3 &  _LC5_A16 & !_LC7_A23
         # !cc2 & !cc3 & !_LC7_A23;

-- Node name is '~1421~2' 
-- Equation name is '~1421~2', location is LC8_A13, type is buried.
-- synthesized logic cell 
_LC8_A13 = LCELL( _EQ043);
  _EQ043 =  cc4 &  _LC1_A23
         # !_LC1_A13 &  _LC1_A23
         # !cc4 & !_LC1_A13 & !_LC2_A16;

-- Node name is ':1421' 
-- Equation name is '_LC4_A23', type is buried 
_LC4_A23 = LCELL( _EQ044);
  _EQ044 =  _LC5_A13
         #  _LC5_A23 & !_LC6_A23
         # !_LC6_A23 &  _LC8_A13;

-- Node name is '~1435~1' 
-- Equation name is '~1435~1', location is LC5_C5, type is buried.
-- synthesized logic cell 
!_LC5_C5 = _LC5_C5~NOT;
_LC5_C5~NOT = LCELL( _EQ045);
  _EQ045 =  ll7
         #  ll8;

-- Node name is ':1435' 
-- Equation name is '_LC6_C5', type is buried 
_LC6_C5  = LCELL( _EQ046);
  _EQ046 =  _LC4_C5 &  _LC5_C5 & !ll6;

-- Node name is ':1448' 
-- Equation name is '_LC4_C5', type is buried 
_LC4_C5  = LCELL( _EQ047);
  _EQ047 = !ll3
         # !ll2
         # !ll5
         # !ll4;

-- Node name is ':1486' 
-- Equation name is '_LC7_C5', type is buried 
!_LC7_C5 = _LC7_C5~NOT;
_LC7_C5~NOT = LCELL( _EQ048);
  _EQ048 = !_LC5_C5
         #  _LC1_C2 &  ll3 &  ll4;

-- Node name is ':1537' 
-- Equation name is '_LC4_C2', type is buried 
_LC4_C2  = LCELL( _EQ049);
  _EQ049 =  _LC2_C4 & !ll6 & !ll8
         # !ll7 & !ll8;

-- Node name is ':1550' 
-- Equation name is '_LC2_C4', type is buried 
_LC2_C4  = LCELL( _EQ050);
  _EQ050 = !ll2 & !ll3
         # !ll5
         # !ll4;

-- Node name is ':1588' 
-- Equation name is '_LC5_C11', type is buried 
!_LC5_C11 = _LC5_C11~NOT;
_LC5_C11~NOT = LCELL( _EQ051);
  _EQ051 =  _LC1_C2 &  ll4 &  ll7
         #  ll8;

-- Node name is '~1591~1' 
-- Equation name is '~1591~1', location is LC1_C2, type is buried.
-- synthesized logic cell 
!_LC1_C2 = _LC1_C2~NOT;
_LC1_C2~NOT = LCELL( _EQ052);
  _EQ052 = !ll6
         # !ll5;

-- Node name is ':1637' 
-- Equation name is '_LC2_C5', type is buried 
_LC2_C5  = LCELL( _EQ053);
  _EQ053 =  _LC8_C5 & !ll6 & !ll7
         # !ll8;

-- Node name is ':1652' 
-- Equation name is '_LC8_C5', type is buried 
_LC8_C5  = LCELL( _EQ054);
  _EQ054 = !ll3 & !ll4
         # !ll2 & !ll4
         # !ll5;

-- Node name is ':1690' 
-- Equation name is '_LC7_C11', type is buried 
!_LC7_C11 = _LC7_C11~NOT;
_LC7_C11~NOT = LCELL( _EQ055);
  _EQ055 =  _LC1_C2 &  ll4
         #  _LC1_C2 &  ll3
         #  ll7;

-- Node name is ':1744' 
-- Equation name is '_LC6_C11', type is buried 
_LC6_C11 = LCELL( _EQ056);
  _EQ056 = !ll5 & !ll6
         #  _LC1_C4 & !ll6
         # !ll7;

-- Node name is ':1756' 
-- Equation name is '_LC1_C4', type is buried 
!_LC1_C4 = _LC1_C4~NOT;
_LC1_C4~NOT = LCELL( _EQ057);
  _EQ057 =  ll4
         #  ll3
         #  ll2;

-- Node name is '~1874~1' 
-- Equation name is '~1874~1', location is LC3_C5, type is buried.
-- synthesized logic cell 
_LC3_C5  = LCELL( _EQ058);
  _EQ058 =  _LC4_C5 &  _LC5_C5 & !ll6
         #  _LC7_C5;

-- Node name is ':1874' 
-- Equation name is '_LC4_C11', type is buried 
_LC4_C11 = LCELL( _EQ059);
  _EQ059 = !_LC8_C11
         #  _LC3_C5;

-- Node name is '~1897~1' 
-- Equation name is '~1897~1', location is LC8_C11, type is buried.
-- synthesized logic cell 
!_LC8_C11 = _LC8_C11~NOT;
_LC8_C11~NOT = LCELL( _EQ060);
  _EQ060 =  _LC4_C2
         #  _LC5_C11;

-- Node name is ':1898' 
-- Equation name is '_LC3_C11', type is buried 
_LC3_C11 = LCELL( _EQ061);
  _EQ061 =  _LC2_C5 &  _LC8_C11
         #  _LC7_C11 &  _LC8_C11
         #  _LC3_C5;

-- Node name is ':1918' 
-- Equation name is '_LC2_C11', type is buried 
_LC2_C11 = LCELL( _EQ062);
  _EQ062 =  _LC2_C5 & !_LC5_C11
         # !_LC5_C11 &  _LC6_C11 & !_LC7_C11;

-- Node name is ':1922' 
-- Equation name is '_LC1_C5', type is buried 
_LC1_C5  = LCELL( _EQ063);
  _EQ063 =  _LC6_C5
         #  _LC4_C2 & !_LC7_C5
         #  _LC2_C11 & !_LC7_C5;

-- Node name is ':1964' 
-- Equation name is '_LC7_A15', type is buried 
_LC7_A15 = LCELL( _EQ064);
  _EQ064 = !_LC1_C11 &  _LC4_A15 & !_LC7_A13 & !md
         # !_LC1_C11 & !_LC4_A15 & !_LC7_A13 &  md;

-- Node name is ':1974' 
-- Equation name is '_LC1_A17', type is buried 
_LC1_A17 = LCELL( _EQ065);
  _EQ065 =  _LC1_A15 & !_LC1_C11 & !_LC7_A13 & !md
         # !_LC1_A15 & !_LC1_C11 & !_LC7_A13 &  md;

-- Node name is ':1984' 
-- Equation name is '_LC6_A15', type is buried 
_LC6_A15 = LCELL( _EQ066);
  _EQ066 = !_LC1_C11 &  _LC5_A15 & !_LC7_A13 & !md
         # !_LC1_C11 & !_LC5_A15 & !_LC7_A13 &  md;



Project Information                         d:\maxplus2\1502d\test12\color.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 15,343K