vga.rpt

几个VHDL实现的源程序及其代码

-- Node name is '|COLOR:17|:1098' 
-- Equation name is '_LC5_C14', type is buried 
_LC5_C14 = LCELL( _EQ033);
  _EQ033 = !_LC1_C14 & !_LC3_C14 & !_LC4_C14 & !_LC8_C14;

-- Node name is '|COLOR:17|:1125' 
-- Equation name is '_LC3_C22', type is buried 
_LC3_C22 = LCELL( _EQ034);
  _EQ034 = !_LC1_C14 & !_LC7_C14 & !_LC8_C14
         # !_LC1_C14 & !_LC3_C14 & !_LC8_C14;

-- Node name is '|COLOR:17|:1152' 
-- Equation name is '_LC4_C22', type is buried 
!_LC4_C22 = _LC4_C22~NOT;
_LC4_C22~NOT = LCELL( _EQ035);
  _EQ035 =  _LC1_C14 & !_LC3_C13
         #  _LC1_C14 &  _LC3_C14
         #  _LC8_C14;

-- Node name is '|COLOR:17|:1182' 
-- Equation name is '_LC1_C17', type is buried 
_LC1_C17 = LCELL( _EQ036);
  _EQ036 = !_LC1_C14
         # !_LC3_C14;

-- Node name is '|COLOR:17|:1231' 
-- Equation name is '_LC5_C17', type is buried 
_LC5_C17 = LCELL( _EQ037);
  _EQ037 = !_LC1_C14 & !_LC3_C14 & !_LC7_C14
         # !_LC8_C14;

-- Node name is '|COLOR:17|:1270' 
-- Equation name is '_LC3_C13', type is buried 
!_LC3_C13 = _LC3_C13~NOT;
_LC3_C13~NOT = LCELL( _EQ038);
  _EQ038 =  _LC1_C13
         #  _LC7_C14;

-- Node name is '|COLOR:17|~1373~1' 
-- Equation name is '_LC5_C22', type is buried 
-- synthesized logic cell 
!_LC5_C22 = _LC5_C22~NOT;
_LC5_C22~NOT = LCELL( _EQ039);
  _EQ039 = !_LC4_C22 &  _LC8_C14
         # !_LC1_C17 & !_LC4_C22;

-- Node name is '|COLOR:17|:1373' 
-- Equation name is '_LC2_C22', type is buried 
_LC2_C22 = LCELL( _EQ040);
  _EQ040 =  _LC3_C22
         #  _LC5_C14
         #  _LC5_C22;

-- Node name is '|COLOR:17|:1397' 
-- Equation name is '_LC1_C22', type is buried 
_LC1_C22 = LCELL( _EQ041);
  _EQ041 =  _LC3_C22
         #  _LC5_C14
         #  _LC5_C17 & !_LC5_C22;

-- Node name is '|COLOR:17|~1421~1' 
-- Equation name is '_LC7_C22', type is buried 
-- synthesized logic cell 
_LC7_C22 = LCELL( _EQ042);
  _EQ042 = !_LC1_C14 &  _LC3_C13 & !_LC5_C17
         # !_LC1_C14 & !_LC3_C14 & !_LC5_C17;

-- Node name is '|COLOR:17|~1421~2' 
-- Equation name is '_LC8_C22', type is buried 
-- synthesized logic cell 
_LC8_C22 = LCELL( _EQ043);
  _EQ043 =  _LC7_C22 &  _LC8_C14
         # !_LC1_C17 &  _LC7_C22
         # !_LC1_C17 & !_LC4_C14 & !_LC8_C14;

-- Node name is '|COLOR:17|:1421' 
-- Equation name is '_LC6_C22', type is buried 
_LC6_C22 = LCELL( _EQ044);
  _EQ044 = !_LC3_C22 &  _LC8_C22
         # !_LC3_C22 &  _LC4_C22
         #  _LC5_C14;

-- Node name is '|COLOR:17|:1435' 
-- Equation name is '_LC7_C20', type is buried 
_LC7_C20 = LCELL( _EQ045);
  _EQ045 = !_LC2_C23 & !_LC3_C23 &  _LC5_C20 & !_LC6_C23;

-- Node name is '|COLOR:17|:1448' 
-- Equation name is '_LC5_C20', type is buried 
_LC5_C20 = LCELL( _EQ046);
  _EQ046 = !_LC3_C21
         # !_LC6_C21
         # !_LC5_C23
         # !_LC4_C21;

-- Node name is '|COLOR:17|~1486~1' 
-- Equation name is '_LC2_C18', type is buried 
-- synthesized logic cell 
!_LC2_C18 = _LC2_C18~NOT;
_LC2_C18~NOT = LCELL( _EQ047);
  _EQ047 = !_LC2_C23 & !_LC3_C23;

-- Node name is '|COLOR:17|:1486' 
-- Equation name is '_LC1_C18', type is buried 
_LC1_C18 = LCELL( _EQ048);
  _EQ048 = !_LC2_C18 & !_LC4_C21
         # !_LC1_C23 & !_LC2_C18
         # !_LC2_C18 & !_LC3_C21;

-- Node name is '|COLOR:17|:1537' 
-- Equation name is '_LC4_C20', type is buried 
!_LC4_C20 = _LC4_C20~NOT;
_LC4_C20~NOT = LCELL( _EQ049);
  _EQ049 =  _LC3_C23 & !_LC6_C20
         #  _LC3_C23 &  _LC6_C23
         #  _LC2_C23;

-- Node name is '|COLOR:17|:1550' 
-- Equation name is '_LC6_C20', type is buried 
!_LC6_C20 = _LC6_C20~NOT;
_LC6_C20~NOT = LCELL( _EQ050);
  _EQ050 =  _LC3_C21 &  _LC4_C21 &  _LC5_C23
         #  _LC4_C21 &  _LC5_C23 &  _LC6_C21;

-- Node name is '|COLOR:17|:1588' 
-- Equation name is '_LC5_C15', type is buried 
!_LC5_C15 = _LC5_C15~NOT;
_LC5_C15~NOT = LCELL( _EQ051);
  _EQ051 =  _LC1_C23 &  _LC3_C23 &  _LC4_C21
         #  _LC2_C23;

-- Node name is '|COLOR:17|~1591~1' 
-- Equation name is '_LC1_C23', type is buried 
-- synthesized logic cell 
!_LC1_C23 = _LC1_C23~NOT;
_LC1_C23~NOT = LCELL( _EQ052);
  _EQ052 = !_LC6_C23
         # !_LC5_C23;

-- Node name is '|COLOR:17|:1637' 
-- Equation name is '_LC3_C20', type is buried 
_LC3_C20 = LCELL( _EQ053);
  _EQ053 = !_LC3_C23 & !_LC6_C23 &  _LC8_C20
         # !_LC2_C23;

-- Node name is '|COLOR:17|:1652' 
-- Equation name is '_LC8_C20', type is buried 
_LC8_C20 = LCELL( _EQ054);
  _EQ054 = !_LC3_C21 & !_LC4_C21
         # !_LC4_C21 & !_LC6_C21
         # !_LC5_C23;

-- Node name is '|COLOR:17|:1690' 
-- Equation name is '_LC7_C15', type is buried 
_LC7_C15 = LCELL( _EQ055);
  _EQ055 = !_LC3_C21 & !_LC3_C23 & !_LC4_C21
         # !_LC1_C23 & !_LC3_C23;

-- Node name is '|COLOR:17|:1744' 
-- Equation name is '_LC4_C23', type is buried 
_LC4_C23 = LCELL( _EQ056);
  _EQ056 = !_LC5_C23 & !_LC6_C23
         #  _LC2_C20 & !_LC6_C23
         # !_LC3_C23;

-- Node name is '|COLOR:17|:1756' 
-- Equation name is '_LC2_C20', type is buried 
!_LC2_C20 = _LC2_C20~NOT;
_LC2_C20~NOT = LCELL( _EQ057);
  _EQ057 =  _LC4_C21
         #  _LC3_C21
         #  _LC6_C21;

-- Node name is '|COLOR:17|~1874~1' 
-- Equation name is '_LC4_C15', type is buried 
-- synthesized logic cell 
_LC4_C15 = LCELL( _EQ058);
  _EQ058 =  _LC1_C18
         #  _LC7_C20;

-- Node name is '|COLOR:17|:1874' 
-- Equation name is '_LC2_C15', type is buried 
_LC2_C15 = LCELL( _EQ059);
  _EQ059 =  _LC1_C18
         #  _LC7_C20
         #  _LC5_C15
         #  _LC4_C20;

-- Node name is '|COLOR:17|~1897~1' 
-- Equation name is '_LC6_C15', type is buried 
-- synthesized logic cell 
_LC6_C15 = LCELL( _EQ060);
  _EQ060 = !_LC4_C20 & !_LC5_C15;

-- Node name is '|COLOR:17|:1898' 
-- Equation name is '_LC3_C15', type is buried 
_LC3_C15 = LCELL( _EQ061);
  _EQ061 =  _LC4_C15
         #  _LC6_C15 &  _LC7_C15
         #  _LC3_C20 &  _LC6_C15;

-- Node name is '|COLOR:17|:1918' 
-- Equation name is '_LC8_C15', type is buried 
_LC8_C15 = LCELL( _EQ062);
  _EQ062 =  _LC4_C23 & !_LC5_C15 & !_LC7_C15
         #  _LC3_C20 & !_LC5_C15;

-- Node name is '|COLOR:17|:1922' 
-- Equation name is '_LC1_C15', type is buried 
_LC1_C15 = LCELL( _EQ063);
  _EQ063 = !_LC1_C18 &  _LC8_C15
         # !_LC1_C18 &  _LC4_C20
         #  _LC7_C20;

-- Node name is '|COLOR:17|:1964' 
-- Equation name is '_LC2_C17', type is buried 
_LC2_C17 = LCELL( _EQ064);
  _EQ064 = !_LC1_C16 & !_LC1_C20 & !_LC6_C17 &  _LC7_C17
         #  _LC1_C16 & !_LC1_C20 & !_LC6_C17 & !_LC7_C17;

-- Node name is '|COLOR:17|:1974' 
-- Equation name is '_LC3_C16', type is buried 
_LC3_C16 = LCELL( _EQ065);
  _EQ065 = !_LC1_C16 & !_LC1_C20 &  _LC6_C16 & !_LC6_C17
         #  _LC1_C16 & !_LC1_C20 & !_LC6_C16 & !_LC6_C17;

-- Node name is '|COLOR:17|:1984' 
-- Equation name is '_LC2_C16', type is buried 
_LC2_C16 = LCELL( _EQ066);
  _EQ066 = !_LC1_C16 & !_LC1_C20 & !_LC6_C17 &  _LC7_C16
         #  _LC1_C16 & !_LC1_C20 & !_LC6_C17 & !_LC7_C16;

-- Node name is '|74161:13|f74161:sub|:9' = '|74161:13|f74161:sub|QA' 
-- Equation name is '_LC4_C16', type is buried 
_LC4_C16 = DFFE(!_LC4_C16, GLOBAL( 1HZ),  VCC,  VCC,  VCC);

-- Node name is '|74161:13|f74161:sub|:87' = '|74161:13|f74161:sub|QB' 
-- Equation name is '_LC5_C16', type is buried 
_LC5_C16 = DFFE( _EQ067, GLOBAL( 1HZ),  VCC,  VCC,  VCC);
  _EQ067 =  _LC4_C16 & !_LC5_C16
         # !_LC4_C16 &  _LC5_C16;

-- Node name is '|74161:13|f74161:sub|:99' = '|74161:13|f74161:sub|QC' 
-- Equation name is '_LC1_C16', type is buried 
_LC1_C16 = DFFE( _EQ068, GLOBAL( 1HZ),  VCC,  VCC,  VCC);
  _EQ068 =  _LC1_C16 & !_LC4_C16
         #  _LC1_C16 & !_LC5_C16
         # !_LC1_C16 &  _LC4_C16 &  _LC5_C16;



Project Information                      c:\windows\desktop\alleda\vga\vga.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 14,357K