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📄 vga.rpt

📁 几个VHDL实现的源程序及其代码
💻 RPT
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   -      6     -    C    22        OR2                0    4    0    1  |COLOR:17|:1421
   -      7     -    C    20       AND2                0    4    0    3  |COLOR:17|:1435
   -      5     -    C    20        OR2                0    4    0    1  |COLOR:17|:1448
   -      2     -    C    18       AND2    s   !       0    2    0    1  |COLOR:17|~1486~1
   -      1     -    C    18        OR2                0    4    0    3  |COLOR:17|:1486
   -      4     -    C    20        OR2        !       0    4    0    3  |COLOR:17|:1537
   -      6     -    C    20        OR2        !       0    4    0    1  |COLOR:17|:1550
   -      5     -    C    15        OR2        !       0    4    0    3  |COLOR:17|:1588
   -      1     -    C    23        OR2    s   !       0    2    0    4  |COLOR:17|~1591~1
   -      3     -    C    20        OR2                0    4    0    2  |COLOR:17|:1637
   -      8     -    C    20        OR2                0    4    0    1  |COLOR:17|:1652
   -      7     -    C    15        OR2                0    4    0    2  |COLOR:17|:1690
   -      4     -    C    23        OR2                0    4    0    1  |COLOR:17|:1744
   -      2     -    C    20        OR2        !       0    3    0    2  |COLOR:17|:1756
   -      4     -    C    15        OR2    s           0    2    0    1  |COLOR:17|~1874~1
   -      2     -    C    15        OR2                0    4    0    1  |COLOR:17|:1874
   -      6     -    C    15       AND2    s           0    2    0    1  |COLOR:17|~1897~1
   -      3     -    C    15        OR2                0    4    0    1  |COLOR:17|:1898
   -      8     -    C    15        OR2                0    4    0    1  |COLOR:17|:1918
   -      1     -    C    15        OR2                0    4    0    1  |COLOR:17|:1922
   -      2     -    C    17        OR2                0    4    1    0  |COLOR:17|:1964
   -      3     -    C    16        OR2                0    4    1    0  |COLOR:17|:1974
   -      2     -    C    16        OR2                0    4    1    0  |COLOR:17|:1984
   -      4     -    C    16       DFFE   +            0    0    0    2  |74161:13|f74161:sub|QA (|74161:13|f74161:sub|:9)
   -      5     -    C    16       DFFE   +            0    1    0    1  |74161:13|f74161:sub|QB (|74161:13|f74161:sub|:87)
   -      1     -    C    16       DFFE   +            0    2    0    5  |74161:13|f74161:sub|QC (|74161:13|f74161:sub|:99)


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:             c:\windows\desktop\alleda\vga\vga.rpt
vga

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
B:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
C:      19/ 96( 19%)     0/ 48(  0%)    25/ 48( 52%)    0/16(  0%)      0/16(  0%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
16:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
17:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
18:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
19:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:             c:\windows\desktop\alleda\vga\vga.rpt
vga

** CLOCK SIGNALS **

Type     Fan-out       Name
DFF         18         |COLOR:17|cc4
DFF          8         |COLOR:17|fs2
DFF          6         |74161:13|f74161:sub|QC
INPUT        4         6MCLK
INPUT        3         1HZ


Device-Specific Information:             c:\windows\desktop\alleda\vga\vga.rpt
vga

** EQUATIONS **

1HZ      : INPUT;
6MCLK    : INPUT;

-- Node name is 'B' 
-- Equation name is 'B', type is output 
B        =  _LC2_C17;

-- Node name is 'G' 
-- Equation name is 'G', type is output 
G        =  _LC2_C16;

-- Node name is 'HS' 
-- Equation name is 'HS', type is output 
HS       = !_LC6_C17;

-- Node name is 'R' 
-- Equation name is 'R', type is output 
R        =  _LC3_C16;

-- Node name is 'VS' 
-- Equation name is 'VS', type is output 
VS       = !_LC1_C20;

-- Node name is '|COLOR:17|:28' = '|COLOR:17|cc0' 
-- Equation name is '_LC1_C13', type is buried 
_LC1_C13 = DFFE(!_LC1_C13,  _LC2_C13,  VCC,  VCC,  VCC);

-- Node name is '|COLOR:17|:27' = '|COLOR:17|cc1' 
-- Equation name is '_LC7_C14', type is buried 
_LC7_C14 = DFFE( _EQ001,  _LC2_C13,  VCC,  VCC,  VCC);
  _EQ001 =  _LC1_C13 & !_LC2_C14 & !_LC7_C14
         # !_LC1_C13 & !_LC2_C14 &  _LC7_C14;

-- Node name is '|COLOR:17|:26' = '|COLOR:17|cc2' 
-- Equation name is '_LC3_C14', type is buried 
_LC3_C14 = DFFE( _EQ002,  _LC2_C13,  VCC,  VCC,  VCC);
  _EQ002 = !_LC2_C14 &  _LC3_C14 & !_LC4_C14
         # !_LC2_C14 & !_LC3_C14 &  _LC4_C14;

-- Node name is '|COLOR:17|:25' = '|COLOR:17|cc3' 
-- Equation name is '_LC1_C14', type is buried 
_LC1_C14 = DFFE( _EQ003,  _LC2_C13,  VCC,  VCC,  VCC);
  _EQ003 =  _LC1_C14 & !_LC2_C14 & !_LC3_C14
         #  _LC1_C14 & !_LC2_C14 & !_LC4_C14
         # !_LC1_C14 & !_LC2_C14 &  _LC3_C14 &  _LC4_C14;

-- Node name is '|COLOR:17|:24' = '|COLOR:17|cc4' 
-- Equation name is '_LC8_C14', type is buried 
_LC8_C14 = DFFE( _EQ004,  _LC2_C13,  VCC,  VCC,  VCC);
  _EQ004 = !_LC2_C14 & !_LC6_C14 &  _LC8_C14
         # !_LC1_C14 & !_LC2_C14 &  _LC8_C14
         #  _LC1_C14 & !_LC2_C14 &  _LC6_C14 & !_LC8_C14;

-- Node name is '|COLOR:17|:22' = '|COLOR:17|fs0' 
-- Equation name is '_LC6_C13', type is buried 
_LC6_C13 = DFFE( _EQ005, GLOBAL( 6MCLK),  VCC,  VCC,  VCC);
  _EQ005 = !_LC2_C13 & !_LC6_C13
         #  _LC5_C13 & !_LC6_C13
         # !_LC4_C13 & !_LC6_C13;

-- Node name is '|COLOR:17|:21' = '|COLOR:17|fs1' 
-- Equation name is '_LC5_C13', type is buried 
_LC5_C13 = DFFE( _EQ006, GLOBAL( 6MCLK),  VCC,  VCC,  VCC);
  _EQ006 = !_LC5_C13 &  _LC6_C13
         #  _LC5_C13 & !_LC6_C13;

-- Node name is '|COLOR:17|:20' = '|COLOR:17|fs2' 
-- Equation name is '_LC2_C13', type is buried 
_LC2_C13 = DFFE( _EQ007, GLOBAL( 6MCLK),  VCC,  VCC,  VCC);
  _EQ007 = !_LC2_C13 &  _LC5_C13 &  _LC6_C13
         #  _LC2_C13 &  _LC5_C13 & !_LC6_C13
         #  _LC2_C13 & !_LC4_C13 & !_LC6_C13
         #  _LC2_C13 & !_LC4_C13 & !_LC5_C13
         #  _LC2_C13 & !_LC5_C13 &  _LC6_C13;

-- Node name is '|COLOR:17|:19' = '|COLOR:17|fs3' 
-- Equation name is '_LC4_C13', type is buried 
_LC4_C13 = DFFE( _EQ008, GLOBAL( 6MCLK),  VCC,  VCC,  VCC);
  _EQ008 = !_LC2_C13 &  _LC4_C13
         #  _LC2_C13 & !_LC4_C13 &  _LC5_C13 &  _LC6_C13
         #  _LC4_C13 &  _LC5_C13 & !_LC6_C13
         #  _LC4_C13 & !_LC5_C13 &  _LC6_C13;

-- Node name is '|COLOR:17|:38' = '|COLOR:17|ll0' 
-- Equation name is '_LC8_C17', type is buried 
_LC8_C17 = DFFE(!_LC8_C17, !_LC8_C14,  VCC,  VCC,  VCC);

-- Node name is '|COLOR:17|:37' = '|COLOR:17|ll1' 
-- Equation name is '_LC8_C21', type is buried 
_LC8_C21 = DFFE( _EQ009, !_LC8_C14,  VCC,  VCC,  VCC);
  _EQ009 = !_LC1_C21 &  _LC8_C17 & !_LC8_C21
         # !_LC1_C21 & !_LC8_C17 &  _LC8_C21;

-- Node name is '|COLOR:17|:36' = '|COLOR:17|ll2' 
-- Equation name is '_LC6_C21', type is buried 
_LC6_C21 = DFFE( _EQ010, !_LC8_C14,  VCC,  VCC,  VCC);
  _EQ010 = !_LC1_C21 & !_LC5_C21 &  _LC6_C21
         # !_LC1_C21 &  _LC5_C21 & !_LC6_C21;

-- Node name is '|COLOR:17|:35' = '|COLOR:17|ll3' 
-- Equation name is '_LC3_C21', type is buried 
_LC3_C21 = DFFE( _EQ011, !_LC8_C14,  VCC,  VCC,  VCC);
  _EQ011 = !_LC1_C21 &  _LC3_C21 & !_LC6_C21
         # !_LC1_C21 &  _LC3_C21 & !_LC5_C21
         # !_LC1_C21 & !_LC3_C21 &  _LC5_C21 &  _LC6_C21;

-- Node name is '|COLOR:17|:34' = '|COLOR:17|ll4' 
-- Equation name is '_LC4_C21', type is buried 
_LC4_C21 = DFFE( _EQ012, !_LC8_C14,  VCC,  VCC,  VCC);
  _EQ012 = !_LC1_C21 &  _LC4_C21 & !_LC7_C21
         # !_LC1_C21 & !_LC3_C21 &  _LC4_C21
         # !_LC1_C21 &  _LC3_C21 & !_LC4_C21 &  _LC7_C21;

-- Node name is '|COLOR:17|:33' = '|COLOR:17|ll5' 
-- Equation name is '_LC5_C23', type is buried 
_LC5_C23 = DFFE( _EQ013, !_LC8_C14,  VCC,  VCC,  VCC);
  _EQ013 = !_LC1_C21 & !_LC2_C21 &  _LC5_C23
         # !_LC1_C21 &  _LC2_C21 & !_LC5_C23;

-- Node name is '|COLOR:17|:32' = '|COLOR:17|ll6' 
-- Equation name is '_LC6_C23', type is buried 
_LC6_C23 = DFFE( _EQ014, !_LC8_C14,  VCC,  VCC,  VCC);
  _EQ014 = !_LC1_C21 & !_LC5_C23 &  _LC6_C23
         # !_LC1_C21 & !_LC2_C21 &  _LC6_C23
         # !_LC1_C21 &  _LC2_C21 &  _LC5_C23 & !_LC6_C23;

-- Node name is '|COLOR:17|:31' = '|COLOR:17|ll7' 
-- Equation name is '_LC3_C23', type is buried 
_LC3_C23 = DFFE( _EQ015, !_LC8_C14,  VCC,  VCC,  VCC);
  _EQ015 = !_LC1_C21 &  _LC3_C23 & !_LC6_C23
         # !_LC1_C21 &  _LC3_C23 & !_LC7_C23
         # !_LC1_C21 & !_LC3_C23 &  _LC6_C23 &  _LC7_C23;

-- Node name is '|COLOR:17|:30' = '|COLOR:17|ll8' 
-- Equation name is '_LC2_C23', type is buried 
_LC2_C23 = DFFE( _EQ016, !_LC8_C14,  VCC,  VCC,  VCC);
  _EQ016 = !_LC1_C21 &  _LC2_C23 & !_LC3_C23
         # !_LC1_C21 &  _LC2_C23 & !_LC8_C23
         # !_LC1_C21 & !_LC2_C23 &  _LC3_C23 &  _LC8_C23;

-- Node name is '|COLOR:17|LPM_ADD_SUB:441|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_C14', type is buried 
_LC4_C14 = LCELL( _EQ017);
  _EQ017 =  _LC1_C13 &  _LC7_C14;

-- Node name is '|COLOR:17|LPM_ADD_SUB:441|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C14', type is buried 
_LC6_C14 = LCELL( _EQ018);
  _EQ018 =  _LC3_C14 &  _LC4_C14;

-- Node name is '|COLOR:17|LPM_ADD_SUB:631|addcore:adder|:75' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C21', type is buried 
_LC5_C21 = LCELL( _EQ019);
  _EQ019 =  _LC8_C17 &  _LC8_C21;

-- Node name is '|COLOR:17|LPM_ADD_SUB:631|addcore:adder|:79' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C21', type is buried 
_LC7_C21 = LCELL( _EQ020);
  _EQ020 =  _LC5_C21 &  _LC6_C21;

-- Node name is '|COLOR:17|LPM_ADD_SUB:631|addcore:adder|:87' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C21', type is buried 
_LC2_C21 = LCELL( _EQ021);
  _EQ021 =  _LC3_C21 &  _LC4_C21 &  _LC5_C21 &  _LC6_C21;

-- Node name is '|COLOR:17|LPM_ADD_SUB:631|addcore:adder|:91' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C23', type is buried 
_LC7_C23 = LCELL( _EQ022);
  _EQ022 =  _LC2_C21 &  _LC5_C23;

-- Node name is '|COLOR:17|LPM_ADD_SUB:631|addcore:adder|:95' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C23', type is buried 
_LC8_C23 = LCELL( _EQ023);
  _EQ023 =  _LC2_C21 &  _LC5_C23 &  _LC6_C23;

-- Node name is '|COLOR:17|:9' = '|COLOR:17|mmd0' 
-- Equation name is '_LC3_C17', type is buried 
_LC3_C17 = DFFE( _EQ024,  _LC1_C16,  VCC,  VCC,  VCC);
  _EQ024 = !_LC3_C17 & !_LC4_C17;

-- Node name is '|COLOR:17|:8' = '|COLOR:17|mmd1' 
-- Equation name is '_LC4_C17', type is buried 
_LC4_C17 = DFFE( _EQ025,  _LC1_C16,  VCC,  VCC,  VCC);
  _EQ025 =  _LC3_C17 & !_LC4_C17;

-- Node name is '|COLOR:17|:233' 
-- Equation name is '_LC7_C16', type is buried 
_LC7_C16 = LCELL( _EQ026);
  _EQ026 =  _LC2_C15 & !_LC2_C22 & !_LC3_C17 &  _LC4_C17
         # !_LC2_C15 &  _LC2_C22 & !_LC3_C17
         #  _LC2_C15 &  _LC3_C17 & !_LC4_C17
         #  _LC2_C22 & !_LC3_C17 & !_LC4_C17;

-- Node name is '|COLOR:17|:245' 
-- Equation name is '_LC6_C16', type is buried 
_LC6_C16 = LCELL( _EQ027);
  _EQ027 =  _LC3_C15 &  _LC3_C17 & !_LC4_C17
         # !_LC1_C22 &  _LC3_C15 & !_LC3_C17 &  _LC4_C17
         #  _LC1_C22 & !_LC3_C15 & !_LC3_C17
         #  _LC1_C22 & !_LC3_C17 & !_LC4_C17;

-- Node name is '|COLOR:17|:257' 
-- Equation name is '_LC7_C17', type is buried 
_LC7_C17 = LCELL( _EQ028);
  _EQ028 =  _LC1_C15 &  _LC3_C17 & !_LC4_C17
         #  _LC1_C15 & !_LC3_C17 &  _LC4_C17 & !_LC6_C22
         # !_LC1_C15 & !_LC3_C17 &  _LC6_C22
         # !_LC3_C17 & !_LC4_C17 &  _LC6_C22;

-- Node name is '|COLOR:17|:410' 
-- Equation name is '_LC2_C14', type is buried 
!_LC2_C14 = _LC2_C14~NOT;
_LC2_C14~NOT = LCELL( _EQ029);
  _EQ029 = !_LC1_C13
         #  _LC1_C17
         # !_LC8_C14
         #  _LC7_C14;

-- Node name is '|COLOR:17|:576' 
-- Equation name is '_LC1_C21', type is buried 
!_LC1_C21 = _LC1_C21~NOT;
_LC1_C21~NOT = LCELL( _EQ030);
  _EQ030 = !_LC1_C20
         # !_LC8_C17
         #  _LC8_C21
         # !_LC2_C20;

-- Node name is '|COLOR:17|:824' 
-- Equation name is '_LC6_C17', type is buried 
!_LC6_C17 = _LC6_C17~NOT;
_LC6_C17~NOT = LCELL( _EQ031);
  _EQ031 = !_LC8_C14
         # !_LC1_C14;

-- Node name is '|COLOR:17|:871' 
-- Equation name is '_LC1_C20', type is buried 
!_LC1_C20 = _LC1_C20~NOT;
_LC1_C20~NOT = LCELL( _EQ032);
  _EQ032 = !_LC1_C23
         # !_LC3_C23
         # !_LC2_C23;

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