hb1.vhd

来自「几个VHDL实现的源程序及其代码」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
entity HB1 is
port(
     DATA: in bit_VECTOR(2 DOWNTO 0);
     y: out bit_vector(2 downto 0));
end HB1;
architecture a of HB1 is
begin
PROCESS(DATA)
BEGIN
CASE DATA IS
WHEN "000"=>Y<="000";
WHEN "001"=>Y<="001";
WHEN "010"=>Y<="001";
WHEN "011"=>Y<="010";
WHEN "100"=>Y<="001";
WHEN "101"=>Y<="010";
WHEN "110"=>Y<="010";
WHEN "111"=>Y<="011";
END CASE;
END PROCESS;
end a;