hb3.vhd

几个VHDL实现的源程序及其代码

library ieee;
use ieee.std_logic_1164.all;
entity HB3 is
port(
     A:  in bit_VECTOR(2 DOWNTO 0);
     B:  in bit_VECTOR(2 DOWNTO 0);
     y: out bit_vector(2 downto 0));
end HB3;

architecture a of HB3 is
SIGNAL DATA : BIT_VECTOR(5 DOWNTO 0);
begin
DATA<=A&B;
PROCESS(DATA)
BEGIN
CASE DATA IS
WHEN "000000"=>Y<="000";
WHEN "001000"=>Y<="001";
WHEN "010000"=>Y<="010";
WHEN "011000"=>Y<="011";
WHEN "100000"=>Y<="100";
WHEN "000001"=>Y<="001";
WHEN "001001"=>Y<="010";
WHEN "010001"=>Y<="011";
WHEN "011001"=>Y<="100";
WHEN "100001"=>Y<="101";
WHEN "000010"=>Y<="010";
WHEN "001010"=>Y<="011";
WHEN "010010"=>Y<="100";
WHEN "011010"=>Y<="101";
WHEN "100010"=>Y<="110";
WHEN "000011"=>Y<="011";
WHEN "001011"=>Y<="100";
WHEN "010011"=>Y<="101";
WHEN "011011"=>Y<="110";
WHEN "100011"=>Y<="111";
WHEN OTHERS=>Y<="000";
END CASE;
END PROCESS;
end a;