hb4.vhd

几个VHDL实现的源程序及其代码

library ieee;
use ieee.std_logic_1164.all;
entity HB4 is
port(
     d: in bit_VECTOR(2 DOWNTO 0);
     lamp0,lamp1: OUT bit);
end HB4;
architecture a of HB4 is
begin
PROCESS(d)
BEGIN
case d is
when "000"=>lamp0<='0';lamp1<='1';
when "001"=>lamp0<='0';lamp1<='1';
when "010"=>lamp0<='0';lamp1<='1';
when "011"=>lamp0<='0';lamp1<='1';
when "100"=>lamp0<='1';lamp1<='0';
when "101"=>lamp0<='1';lamp1<='0';
when "110"=>lamp0<='1';lamp1<='0';
when "111"=>lamp0<='1';lamp1<='0';
end case;
end process;
end a;