hb2.vhd

几个VHDL实现的源程序及其代码

library ieee;
use ieee.std_logic_1164.all;
entity HB2 is
port(
     DATA: in bit_VECTOR(3 DOWNTO 0);
     y: out bit_vector(2 downto 0));
end HB2;
architecture a of HB2 is
begin
PROCESS(DATA)
BEGIN
CASE DATA IS
WHEN "0000"=>Y<="000";
WHEN "0001"=>Y<="001";
WHEN "0010"=>Y<="001";
WHEN "0011"=>Y<="010";
WHEN "0100"=>Y<="001";
WHEN "0101"=>Y<="010";
WHEN "0110"=>Y<="010";
WHEN "0111"=>Y<="011";
WHEN "1000"=>Y<="001";
WHEN "1001"=>Y<="010";
WHEN "1010"=>Y<="010";
WHEN "1011"=>Y<="011";
WHEN "1100"=>Y<="010";
WHEN "1101"=>Y<="011";
WHEN "1110"=>Y<="011";
WHEN "1111"=>Y<="100";
END CASE;
END PROCESS;
end a;