vote7.rpt

几个VHDL实现的源程序及其代码

-- synthesized logic cell 
_LC3_B17 = LCELL( _EQ032);
  _EQ032 = !_LC1_B23 &  _LC5_B17;

-- Node name is '|HB3:3|~475~1' 
-- Equation name is '_LC5_B21', type is buried 
-- synthesized logic cell 
!_LC5_B21 = _LC5_B21~NOT;
_LC5_B21~NOT = LCELL( _EQ033);
  _EQ033 = !_LC3_B13 &  _LC3_B23
         # !_LC2_B17 &  _LC3_B23;

-- Node name is '|HB3:3|~475~2' 
-- Equation name is '_LC8_B21', type is buried 
-- synthesized logic cell 
!_LC8_B21 = _LC8_B21~NOT;
_LC8_B21~NOT = LCELL( _EQ034);
  _EQ034 = !_LC2_B17 &  _LC2_B18 &  _LC3_B23
         # !_LC3_B13 &  _LC3_B23;

-- Node name is '|HB3:3|:475' 
-- Equation name is '_LC2_B21', type is buried 
!_LC2_B21 = _LC2_B21~NOT;
_LC2_B21~NOT = LCELL( _EQ035);
  _EQ035 = !_LC4_B17 & !_LC5_B13
         # !_LC4_B17 & !_LC4_B21
         # !_LC5_B21;

-- Node name is '|HB3:3|~486~1' 
-- Equation name is '_LC1_B17', type is buried 
-- synthesized logic cell 
_LC1_B17 = LCELL( _EQ036);
  _EQ036 =  _LC5_B17
         #  _LC1_B23
         # !_LC1_B18
         # !_LC2_B16;

-- Node name is '|HB3:3|~502~1' 
-- Equation name is '_LC3_B13', type is buried 
-- synthesized logic cell 
!_LC3_B13 = _LC3_B13~NOT;
_LC3_B13~NOT = LCELL( _EQ037);
  _EQ037 =  _LC1_B18 & !_LC1_B23 & !_LC2_B16 & !_LC5_B17;

-- Node name is '|HB3:3|~518~1' 
-- Equation name is '_LC3_B20', type is buried 
-- synthesized logic cell 
_LC3_B20 = LCELL( _EQ038);
  _EQ038 =  _LC2_B17
         # !_LC2_B18;

-- Node name is '|HB3:3|~534~1' 
-- Equation name is '_LC2_B17', type is buried 
-- synthesized logic cell 
_LC2_B17 = LCELL( _EQ039);
  _EQ039 = !_LC4_B18 &  _LC7_B17
         #  _LC1_B23
         #  _LC1_B18;

-- Node name is '|HB3:3|~534~2' 
-- Equation name is '_LC2_B20', type is buried 
-- synthesized logic cell 
!_LC2_B20 = _LC2_B20~NOT;
_LC2_B20~NOT = LCELL( _EQ040);
  _EQ040 = !_LC2_B17 & !_LC2_B18;

-- Node name is '|HB3:3|~539~1' 
-- Equation name is '_LC2_B15', type is buried 
-- synthesized logic cell 
!_LC2_B15 = _LC2_B15~NOT;
_LC2_B15~NOT = LCELL( _EQ041);
  _EQ041 = !_LC2_B17 & !_LC3_B23;

-- Node name is '|HB3:3|~539~2' 
-- Equation name is '_LC8_B17', type is buried 
-- synthesized logic cell 
!_LC8_B17 = _LC8_B17~NOT;
_LC8_B17~NOT = LCELL( _EQ042);
  _EQ042 = !_LC2_B15
         # !_LC3_B13 & !_LC3_B23
         # !_LC1_B17 & !_LC3_B23;

-- Node name is '|HB3:3|:539' 
-- Equation name is '_LC6_B17', type is buried 
!_LC6_B17 = _LC6_B17~NOT;
_LC6_B17~NOT = LCELL( _EQ043);
  _EQ043 = !_LC2_B21 &  _LC3_B23
         # !_LC2_B21 & !_LC3_B17
         # !_LC8_B17;

-- Node name is '|HB3:3|:546' 
-- Equation name is '_LC6_B14', type is buried 
!_LC6_B14 = _LC6_B14~NOT;
_LC6_B14~NOT = LCELL( _EQ044);
  _EQ044 = !_LC6_B13 & !_LC8_B13
         # !_LC1_B18 & !_LC6_B13
         # !_LC2_B16 & !_LC6_B13;

-- Node name is '|HB3:3|~558~1' 
-- Equation name is '_LC8_B14', type is buried 
-- synthesized logic cell 
_LC8_B14 = LCELL( _EQ045);
  _EQ045 = !_LC4_B14 & !_LC5_B14 &  _LC6_B14
         #  _LC2_B13;

-- Node name is '|HB3:3|:558' 
-- Equation name is '_LC3_B14', type is buried 
_LC3_B14 = LCELL( _EQ046);
  _EQ046 =  _LC8_B14
         # !_LC1_B18 & !_LC2_B18 &  _LC8_B13;

-- Node name is '|HB3:3|:570' 
-- Equation name is '_LC6_B21', type is buried 
_LC6_B21 = LCELL( _EQ047);
  _EQ047 = !_LC1_B13 &  _LC3_B14
         # !_LC5_B13;

-- Node name is '|HB3:3|~593~1' 
-- Equation name is '_LC7_B21', type is buried 
-- synthesized logic cell 
_LC7_B21 = LCELL( _EQ048);
  _EQ048 =  _LC2_B17 &  _LC3_B23
         #  _LC2_B17 & !_LC3_B17
         #  _LC2_B18 &  _LC3_B23
         #  _LC2_B18 & !_LC3_B17
         # !_LC3_B17 & !_LC3_B23;

-- Node name is '|HB3:3|:593' 
-- Equation name is '_LC1_B21', type is buried 
_LC1_B21 = LCELL( _EQ049);
  _EQ049 = !_LC4_B17 &  _LC6_B21 &  _LC7_B21
         #  _LC7_B21 & !_LC8_B21;

-- Node name is '|HB3:3|:594' 
-- Equation name is '_LC4_B15', type is buried 
_LC4_B15 = LCELL( _EQ050);
  _EQ050 =  _LC1_B21
         # !_LC3_B13 & !_LC3_B23
         # !_LC1_B17 & !_LC3_B23;

-- Node name is '|HB3:3|:612' 
-- Equation name is '_LC7_B13', type is buried 
_LC7_B13 = LCELL( _EQ051);
  _EQ051 =  _LC4_B14
         #  _LC1_B23 &  _LC2_B23 &  _LC5_B17;

-- Node name is '|HB3:3|:618' 
-- Equation name is '_LC2_B14', type is buried 
_LC2_B14 = LCELL( _EQ052);
  _EQ052 = !_LC1_B18 & !_LC2_B18 &  _LC8_B13
         # !_LC2_B18 &  _LC7_B13
         #  _LC7_B13 & !_LC8_B13
         #  _LC1_B18 &  _LC7_B13;

-- Node name is '|HB3:3|:632' 
-- Equation name is '_LC3_B21', type is buried 
_LC3_B21 = LCELL( _EQ053);
  _EQ053 =  _LC1_B13 &  _LC2_B16
         # !_LC1_B13 & !_LC2_B13 &  _LC2_B14
         # !_LC2_B13 &  _LC2_B14 &  _LC2_B16;

-- Node name is '|HB3:3|:638' 
-- Equation name is '_LC4_B20', type is buried 
_LC4_B20 = LCELL( _EQ054);
  _EQ054 = !_LC1_B18 &  _LC2_B18 & !_LC4_B13
         #  _LC3_B21 &  _LC4_B13
         #  _LC1_B18 &  _LC3_B21
         #  _LC2_B18 &  _LC3_B21;

-- Node name is '|HB3:3|:644' 
-- Equation name is '_LC5_B20', type is buried 
_LC5_B20 = LCELL( _EQ055);
  _EQ055 =  _LC1_B17 &  _LC3_B17 &  _LC3_B23
         #  _LC1_B17 &  _LC4_B20
         # !_LC3_B23 &  _LC4_B20;

-- Node name is '|HB3:3|:650' 
-- Equation name is '_LC6_B20', type is buried 
_LC6_B20 = LCELL( _EQ056);
  _EQ056 = !_LC3_B13 &  _LC3_B20 &  _LC3_B23
         #  _LC3_B20 &  _LC5_B20
         # !_LC3_B23 &  _LC5_B20;

-- Node name is '|HB3:3|:656' 
-- Equation name is '_LC7_B20', type is buried 
_LC7_B20 = LCELL( _EQ057);
  _EQ057 = !_LC2_B20 &  _LC3_B23
         #  _LC3_B23 &  _LC6_B20
         # !_LC3_B17 &  _LC6_B20;

-- Node name is '|HB3:3|:662' 
-- Equation name is '_LC8_B20', type is buried 
_LC8_B20 = LCELL( _EQ058);
  _EQ058 = !_LC1_B17 &  _LC3_B13 & !_LC3_B23
         #  _LC3_B13 &  _LC7_B20
         #  _LC3_B23 &  _LC7_B20;

-- Node name is '|HB3:3|:665' 
-- Equation name is '_LC1_B20', type is buried 
_LC1_B20 = LCELL( _EQ059);
  _EQ059 = !_LC2_B17 &  _LC2_B18 & !_LC3_B23
         #  _LC2_B17 &  _LC8_B20
         #  _LC2_B18 &  _LC8_B20
         #  _LC3_B23 &  _LC8_B20;

-- Node name is '|HB4:12|:97' 
-- Equation name is '_LC8_B15', type is buried 
_LC8_B15 = LCELL( _EQ060);
  _EQ060 =  _LC1_B20 &  _LC2_B15 &  _LC4_B15 & !_LC6_B17;

-- Node name is '|HB4:12|:107' 
-- Equation name is '_LC5_B15', type is buried 
_LC5_B15 = LCELL( _EQ061);
  _EQ061 = !_LC1_B20 &  _LC2_B15 &  _LC4_B15 & !_LC6_B17;

-- Node name is '|HB4:12|:117' 
-- Equation name is '_LC7_B15', type is buried 
_LC7_B15 = LCELL( _EQ062);
  _EQ062 =  _LC1_B20 & !_LC4_B15 & !_LC6_B17
         #  _LC1_B20 & !_LC2_B15 & !_LC6_B17;

-- Node name is '|HB4:12|:127' 
-- Equation name is '_LC6_B15', type is buried 
_LC6_B15 = LCELL( _EQ063);
  _EQ063 = !_LC1_B20 & !_LC4_B15 & !_LC6_B17
         # !_LC1_B20 & !_LC2_B15 & !_LC6_B17;

-- Node name is '|HB4:12|:132' 
-- Equation name is '_LC1_B15', type is buried 
_LC1_B15 = LCELL( _EQ064);
  _EQ064 = !_LC5_B15 & !_LC6_B15 & !_LC7_B15 & !_LC8_B15;

-- Node name is '|HB4:12|:154' 
-- Equation name is '_LC3_B15', type is buried 
_LC3_B15 = LCELL( _EQ065);
  _EQ065 =  _LC5_B15
         #  _LC6_B15
         #  _LC7_B15
         #  _LC8_B15;



Project Information                         d:\edaplay\digital\test6\vote7.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 14,094K