📄 vote7.rpt
字号:
- 7 - B 20 OR2 0 4 0 1 |HB3:3|:656
- 8 - B 20 OR2 0 4 0 1 |HB3:3|:662
- 1 - B 20 OR2 0 4 0 4 |HB3:3|:665
- 8 - B 15 AND2 0 4 0 2 |HB4:12|:97
- 5 - B 15 AND2 0 4 0 2 |HB4:12|:107
- 7 - B 15 OR2 0 4 0 2 |HB4:12|:117
- 6 - B 15 OR2 0 4 0 2 |HB4:12|:127
- 1 - B 15 AND2 0 4 1 0 |HB4:12|:132
- 3 - B 15 OR2 0 4 1 0 |HB4:12|:154
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\edaplay\digital\test6\vote7.rpt
vote7
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 11/ 96( 11%) 0/ 48( 0%) 28/ 48( 58%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
C: 7/ 96( 7%) 0/ 48( 0%) 0/ 48( 0%) 5/16( 31%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\edaplay\digital\test6\vote7.rpt
vote7
** EQUATIONS **
DATA0 : INPUT;
DATA1 : INPUT;
DATA2 : INPUT;
DATA3 : INPUT;
DATA4 : INPUT;
DATA5 : INPUT;
DATA6 : INPUT;
-- Node name is 'lamp0'
-- Equation name is 'lamp0', type is output
lamp0 = _LC1_B15;
-- Node name is 'lamp1'
-- Equation name is 'lamp1', type is output
lamp1 = _LC3_B15;
-- Node name is '|HB1:10|:181'
-- Equation name is '_LC1_B23', type is buried
_LC1_B23 = LCELL( _EQ001);
_EQ001 = DATA0 & DATA1
# DATA0 & DATA2
# DATA1 & DATA2;
-- Node name is '|HB1:10|:199'
-- Equation name is '_LC2_B23', type is buried
_LC2_B23 = LCELL( _EQ002);
_EQ002 = !DATA0 & !DATA1
# DATA0 & DATA1 & DATA2
# !DATA0 & !DATA2
# !DATA1 & !DATA2;
-- Node name is '|HB1:10|:205'
-- Equation name is '_LC3_B23', type is buried
_LC3_B23 = LCELL( _EQ003);
_EQ003 = DATA0 & DATA1 & DATA2
# !DATA0 & !DATA1 & DATA2
# !DATA0 & DATA1 & !DATA2
# DATA0 & !DATA1 & !DATA2;
-- Node name is '|HB2:11|:289'
-- Equation name is '_LC3_B18', type is buried
!_LC3_B18 = _LC3_B18~NOT;
_LC3_B18~NOT = LCELL( _EQ004);
_EQ004 = !DATA5
# DATA6
# DATA4
# DATA3;
-- Node name is '|HB2:11|:301'
-- Equation name is '_LC4_B18', type is buried
!_LC4_B18 = _LC4_B18~NOT;
_LC4_B18~NOT = LCELL( _EQ005);
_EQ005 = !DATA4
# !DATA3
# DATA5
# DATA6;
-- Node name is '|HB2:11|:337'
-- Equation name is '_LC5_B18', type is buried
_LC5_B18 = LCELL( _EQ006);
_EQ006 = !DATA3 & !DATA4 & !DATA5 & !DATA6;
-- Node name is '|HB2:11|~342~1'
-- Equation name is '_LC3_B16', type is buried
-- synthesized logic cell
!_LC3_B16 = _LC3_B16~NOT;
_LC3_B16~NOT = LCELL( _EQ007);
_EQ007 = DATA3 & !DATA4
# !DATA4 & DATA5
# !DATA4 & !DATA6
# !DATA3 & DATA4
# !DATA3 & DATA5
# !DATA3 & !DATA6
# DATA4 & !DATA5
# DATA3 & !DATA5
# !DATA5 & !DATA6
# DATA4 & DATA6
# DATA3 & DATA6
# DATA5 & DATA6;
-- Node name is '|HB2:11|~342~2'
-- Equation name is '_LC1_B16', type is buried
-- synthesized logic cell
_LC1_B16 = LCELL( _EQ008);
_EQ008 = !_LC3_B16 & !_LC6_B16 & !_LC7_B16 & _LC8_B16;
-- Node name is '|HB2:11|~342~3'
-- Equation name is '_LC7_B17', type is buried
-- synthesized logic cell
_LC7_B17 = LCELL( _EQ009);
_EQ009 = _LC1_B16 & !_LC3_B18;
-- Node name is '|HB2:11|:342'
-- Equation name is '_LC5_B17', type is buried
_LC5_B17 = LCELL( _EQ010);
_EQ010 = !_LC4_B18 & _LC7_B17;
-- Node name is '|HB2:11|:361'
-- Equation name is '_LC7_B16', type is buried
!_LC7_B16 = _LC7_B16~NOT;
_LC7_B16~NOT = LCELL( _EQ011);
_EQ011 = !DATA6
# DATA3 & DATA4 & DATA5
# !DATA3 & !DATA4 & !DATA5;
-- Node name is '|HB2:11|~373~1'
-- Equation name is '_LC6_B16', type is buried
-- synthesized logic cell
!_LC6_B16 = _LC6_B16~NOT;
_LC6_B16~NOT = LCELL( _EQ012);
_EQ012 = !DATA5
# DATA6
# !DATA3 & !DATA4
# DATA3 & DATA4;
-- Node name is '|HB2:11|~390~1'
-- Equation name is '_LC8_B16', type is buried
-- synthesized logic cell
_LC8_B16 = LCELL( _EQ013);
_EQ013 = DATA3 & DATA4
# DATA5
# DATA6;
-- Node name is '|HB2:11|:390'
-- Equation name is '_LC1_B18', type is buried
_LC1_B18 = LCELL( _EQ014);
_EQ014 = DATA3 & DATA5 & !DATA6
# DATA4 & DATA5 & !DATA6
# DATA3 & DATA4 & !DATA6
# DATA3 & !DATA5 & DATA6
# DATA4 & !DATA5 & DATA6
# DATA3 & DATA4 & !DATA5
# !DATA4 & DATA5 & DATA6
# DATA3 & !DATA4 & DATA5
# !DATA3 & DATA4 & DATA5;
-- Node name is '|HB2:11|:414'
-- Equation name is '_LC4_B16', type is buried
!_LC4_B16 = _LC4_B16~NOT;
_LC4_B16~NOT = LCELL( _EQ015);
_EQ015 = !DATA3 & !DATA4
# !DATA6
# DATA3 & DATA4 & DATA5
# !DATA4 & !DATA5
# !DATA3 & !DATA5;
-- Node name is '|HB2:11|:415'
-- Equation name is '_LC5_B16', type is buried
!_LC5_B16 = _LC5_B16~NOT;
_LC5_B16~NOT = LCELL( _EQ016);
_EQ016 = !_LC3_B16 & !_LC4_B16;
-- Node name is '|HB2:11|:432'
-- Equation name is '_LC2_B16', type is buried
!_LC2_B16 = _LC2_B16~NOT;
_LC2_B16~NOT = LCELL( _EQ017);
_EQ017 = !_LC3_B18 & !_LC5_B16
# !_LC3_B18 & _LC6_B16
# _LC4_B18;
-- Node name is '|HB2:11|~433~1'
-- Equation name is '_LC6_B18', type is buried
-- synthesized logic cell
!_LC6_B18 = _LC6_B18~NOT;
_LC6_B18~NOT = LCELL( _EQ018);
_EQ018 = !DATA3 & !DATA4
# DATA3 & DATA4
# DATA5
# DATA6;
-- Node name is '|HB2:11|:438'
-- Equation name is '_LC2_B18', type is buried
!_LC2_B18 = _LC2_B18~NOT;
_LC2_B18~NOT = LCELL( _EQ019);
_EQ019 = _LC5_B18
# !_LC2_B16 & !_LC6_B18;
-- Node name is '|HB3:3|:230'
-- Equation name is '_LC6_B13', type is buried
!_LC6_B13 = _LC6_B13~NOT;
_LC6_B13~NOT = LCELL( _EQ020);
_EQ020 = !_LC5_B17
# !_LC1_B23
# !_LC2_B23;
-- Node name is '|HB3:3|~246~1'
-- Equation name is '_LC8_B13', type is buried
-- synthesized logic cell
_LC8_B13 = LCELL( _EQ021);
_EQ021 = _LC1_B23 & _LC2_B23 & !_LC5_B17;
-- Node name is '|HB3:3|:262'
-- Equation name is '_LC4_B14', type is buried
_LC4_B14 = LCELL( _EQ022);
_EQ022 = _LC1_B18 & !_LC2_B16 & _LC8_B13;
-- Node name is '|HB3:3|:278'
-- Equation name is '_LC5_B14', type is buried
!_LC5_B14 = _LC5_B14~NOT;
_LC5_B14~NOT = LCELL( _EQ023);
_EQ023 = !_LC8_B13
# _LC1_B18
# !_LC2_B18;
-- Node name is '|HB3:3|:281'
-- Equation name is '_LC7_B14', type is buried
!_LC7_B14 = _LC7_B14~NOT;
_LC7_B14~NOT = LCELL( _EQ024);
_EQ024 = !_LC4_B14 & !_LC5_B14 & !_LC6_B14;
-- Node name is '|HB3:3|:310'
-- Equation name is '_LC2_B13', type is buried
!_LC2_B13 = _LC2_B13~NOT;
_LC2_B13~NOT = LCELL( _EQ025);
_EQ025 = !_LC5_B17
# !_LC1_B23
# _LC2_B23;
-- Node name is '|HB3:3|:315'
-- Equation name is '_LC1_B14', type is buried
!_LC1_B14 = _LC1_B14~NOT;
_LC1_B14~NOT = LCELL( _EQ026);
_EQ026 = !_LC1_B18 & !_LC2_B18 & _LC8_B13
# !_LC7_B14;
-- Node name is '|HB3:3|~326~1'
-- Equation name is '_LC1_B13', type is buried
-- synthesized logic cell
_LC1_B13 = LCELL( _EQ027);
_EQ027 = _LC1_B18 & !_LC4_B13;
-- Node name is '|HB3:3|:345'
-- Equation name is '_LC4_B21', type is buried
!_LC4_B21 = _LC4_B21~NOT;
_LC4_B21~NOT = LCELL( _EQ028);
_EQ028 = !_LC1_B13 & !_LC1_B14 & !_LC2_B13;
-- Node name is '|HB3:3|~374~1'
-- Equation name is '_LC4_B13', type is buried
-- synthesized logic cell
!_LC4_B13 = _LC4_B13~NOT;
_LC4_B13~NOT = LCELL( _EQ029);
_EQ029 = _LC1_B23 & !_LC2_B23 & !_LC5_B17;
-- Node name is '|HB3:3|~395~1'
-- Equation name is '_LC5_B13', type is buried
-- synthesized logic cell
!_LC5_B13 = _LC5_B13~NOT;
_LC5_B13~NOT = LCELL( _EQ030);
_EQ030 = !_LC1_B18 & !_LC4_B13;
-- Node name is '|HB3:3|~409~1'
-- Equation name is '_LC4_B17', type is buried
-- synthesized logic cell
!_LC4_B17 = _LC4_B17~NOT;
_LC4_B17~NOT = LCELL( _EQ031);
_EQ031 = !_LC3_B23
# _LC1_B17 & !_LC3_B17;
-- Node name is '|HB3:3|~470~1'
-- Equation name is '_LC3_B17', type is buried
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