speaker.vhd

几个VHDL实现的源程序及其代码

library ieee;
use ieee.std_logic_1164.all;
entity speaker is
  port(clk1:in std_logic;
       tone1:in integer range 0 to 16#7ff#;
       spks:out std_logic);
end;
architecture one of speaker is 
   signal preclk,fullspks:std_logic;
begin

divideclk:process(clk1)      --11
  variable count4:integer range 0 to 15;
  begin
    preclk<='0';
    if count4>11 then
       preclk<='1';
       count4:=0;
    elsif clk1'event and clk1='1' then
        count4:=count4+1;
    end if;
  end process;

genspks:process(preclk,tone1)
    variable count11:integer range 0 to 16#7ff#;  
begin
  if preclk'event and preclk='1' then
    if count11=16#7ff# then
       count11:=tone1;
       fullspks<='1';
    else
       count11:=count11+1;
       fullspks<='0';
    end if;
  end if;
end process;

delayspks:process(fullspks)
   variable count2:std_logic;
begin
   if fullspks'event and fullspks='1' then
      count2:=not count2;
      if count2='1' then spks<='1';
      else spks<='0';
      end if;
   end if;
end process;
end;