📄 rs232.rpt
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_LC2_C12~NOT = LCELL( _EQ067);
_EQ067 = !_LC6_C12
# !_LC2_C6;
-- Node name is '|SPEAKER:20|LPM_ADD_SUB:166|addcore:adder|:99' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_C12', type is buried
!_LC1_C12 = _LC1_C12~NOT;
_LC1_C12~NOT = LCELL( _EQ068);
_EQ068 = !_LC8_C12
# !_LC2_C12;
-- Node name is '|SPEAKER:20|LPM_ADD_SUB:166|addcore:adder|:103' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C7', type is buried
!_LC2_C7 = _LC2_C7~NOT;
_LC2_C7~NOT = LCELL( _EQ069);
_EQ069 = !_LC4_C7
# !_LC1_C12;
-- Node name is '|SPEAKER:20|LPM_ADD_SUB:166|addcore:adder|:107' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C7', type is buried
!_LC3_C7 = _LC3_C7~NOT;
_LC3_C7~NOT = LCELL( _EQ070);
_EQ070 = !_LC5_C7
# !_LC2_C7;
-- Node name is '|SPEAKER:20|LPM_ADD_SUB:166|addcore:adder|:111' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_C7', type is buried
!_LC1_C7 = _LC1_C7~NOT;
_LC1_C7~NOT = LCELL( _EQ071);
_EQ071 = !_LC8_C7
# !_LC3_C7;
-- Node name is '|SPEAKER:20|:13'
-- Equation name is '_LC2_C11', type is buried
_LC2_C11 = DFFE(!_LC1_C11, _LC3_C10, VCC, VCC, VCC);
-- Node name is '|SPEAKER:20|:27'
-- Equation name is '_LC1_C9', type is buried
_LC1_C9 = LCELL( _EQ072);
_EQ072 = _LC4_C9 & _LC5_C9;
-- Node name is '|SPEAKER:20|:107'
-- Equation name is '_LC6_C10', type is buried
!_LC6_C10 = _LC6_C10~NOT;
_LC6_C10~NOT = LCELL( _EQ073);
_EQ073 = !_LC8_C10
# !_LC5_C10
# !_LC4_C10
# !_LC1_C7;
-- Node name is '|TONETABA:23|:462'
-- Equation name is '_LC6_C7', type is buried
!_LC6_C7 = _LC6_C7~NOT;
_LC6_C7~NOT = LCELL( _EQ074);
_EQ074 = !_LC4_B8
# !_LC1_B8
# !_LC3_B8
# _LC2_B2;
-- Node name is '|TONETABA:23|:542'
-- Equation name is '_LC7_C10', type is buried
!_LC7_C10 = _LC7_C10~NOT;
_LC7_C10~NOT = LCELL( _EQ075);
_EQ075 = _LC4_B8
# !_LC1_B8
# !_LC3_B8
# _LC2_B2;
-- Node name is '|TONETABA:23|~562~1'
-- Equation name is '_LC1_B11', type is buried
-- synthesized logic cell
_LC1_B11 = LCELL( _EQ076);
_EQ076 = !_LC6_B11
# _LC7_B11
# _LC8_B11;
-- Node name is '|TONETABA:23|~562~2'
-- Equation name is '_LC2_B2', type is buried
-- synthesized logic cell
_LC2_B2 = LCELL( _EQ077);
_EQ077 = _LC7_B2
# !_LC8_B2
# _LC1_B11;
-- Node name is '|TONETABA:23|:582'
-- Equation name is '_LC6_C3', type is buried
!_LC6_C3 = _LC6_C3~NOT;
_LC6_C3~NOT = LCELL( _EQ078);
_EQ078 = _LC4_B8
# _LC1_B8
# !_LC3_B8
# _LC2_B2;
-- Node name is '|TONETABA:23|:602'
-- Equation name is '_LC5_C3', type is buried
_LC5_C3 = LCELL( _EQ079);
_EQ079 = !_LC1_B8 & !_LC2_B2 & !_LC3_B8 & !_LC4_B8;
-- Node name is '|TONETABA:23|:659'
-- Equation name is '_LC2_C10', type is buried
_LC2_C10 = LCELL( _EQ080);
_EQ080 = _LC1_C10 & !_LC7_C10
# _LC5_C3;
-- Node name is '|TONETABA:23|~661~1'
-- Equation name is '_LC1_C10', type is buried
-- synthesized logic cell
_LC1_C10 = LCELL( _EQ081);
_EQ081 = _LC2_B2
# _LC1_B8 & _LC3_B8
# !_LC1_B8 & !_LC3_B8 & !_LC4_B8;
-- Node name is '|TONETABA:23|:686'
-- Equation name is '_LC7_C7', type is buried
_LC7_C7 = LCELL( _EQ082);
_EQ082 = _LC1_C4 & !_LC6_C7
# _LC5_C3;
-- Node name is '|TONETABA:23|:713'
-- Equation name is '_LC4_C12', type is buried
_LC4_C12 = LCELL( _EQ083);
_EQ083 = _LC2_B2
# _LC1_B8 & !_LC3_B8
# !_LC3_B8 & !_LC4_B8
# !_LC1_B8 & _LC3_B8 & _LC4_B8;
-- Node name is '|TONETABA:23|:740'
-- Equation name is '_LC1_C3', type is buried
_LC1_C3 = LCELL( _EQ084);
_EQ084 = _LC3_C3 & !_LC7_C3
# _LC6_C3
# _LC5_C3;
-- Node name is '|TONETABA:23|:755'
-- Equation name is '_LC3_C12', type is buried
_LC3_C12 = LCELL( _EQ085);
_EQ085 = !_LC4_B8
# _LC2_B2
# !_LC1_B8 & !_LC3_B8;
-- Node name is '|TONETABA:23|:767'
-- Equation name is '_LC7_C12', type is buried
_LC7_C12 = LCELL( _EQ086);
_EQ086 = _LC2_B2
# !_LC1_B8 & !_LC3_B8
# !_LC3_B8 & !_LC4_B8;
-- Node name is '|TONETABA:23|:794'
-- Equation name is '_LC5_C12', type is buried
_LC5_C12 = LCELL( _EQ087);
_EQ087 = _LC1_C4 & _LC3_C12 & !_LC7_C10
# _LC5_C3;
-- Node name is '|TONETABA:23|:814'
-- Equation name is '_LC3_C3', type is buried
_LC3_C3 = LCELL( _EQ088);
_EQ088 = !_LC4_B8
# _LC2_B2
# _LC1_B8 & !_LC3_B8;
-- Node name is '|TONETABA:23|:821'
-- Equation name is '_LC2_C3', type is buried
_LC2_C3 = LCELL( _EQ089);
_EQ089 = _LC3_C3 & !_LC6_C3
# !_LC6_C3 & _LC7_C3
# _LC5_C3;
-- Node name is '|TONETABA:23|:836'
-- Equation name is '_LC5_C6', type is buried
_LC5_C6 = LCELL( _EQ090);
_EQ090 = !_LC4_B8
# _LC2_B2
# _LC1_B8 & _LC3_B8
# !_LC1_B8 & !_LC3_B8;
-- Node name is '|TONETABA:23|:848'
-- Equation name is '_LC6_C6', type is buried
_LC6_C6 = LCELL( _EQ091);
_EQ091 = !_LC1_C4
# _LC5_C3
# _LC5_C6 & !_LC7_C10;
-- Node name is '|TONETABA:23|:875'
-- Equation name is '_LC1_C6', type is buried
_LC1_C6 = LCELL( _EQ092);
_EQ092 = _LC2_B2
# _LC1_B8 & _LC3_B8
# _LC3_B8 & _LC4_B8
# !_LC1_B8 & !_LC3_B8 & !_LC4_B8;
-- Node name is '|TONETABA:23|~877~1'
-- Equation name is '_LC1_C4', type is buried
-- synthesized logic cell
!_LC1_C4 = _LC1_C4~NOT;
_LC1_C4~NOT = LCELL( _EQ093);
_EQ093 = !_LC1_B8 & !_LC2_B2 & _LC3_B8 & !_LC4_B8
# _LC1_B8 & !_LC2_B2 & !_LC3_B8 & !_LC4_B8;
-- Node name is '|TONETABA:23|:917'
-- Equation name is '_LC3_C4', type is buried
_LC3_C4 = LCELL( _EQ094);
_EQ094 = !_LC2_B2 & _LC4_B8;
-- Node name is '|TONETABA:23|:931'
-- Equation name is '_LC2_C4', type is buried
_LC2_C4 = LCELL( _EQ095);
_EQ095 = _LC1_C4 & _LC3_C4 & !_LC5_C3 & !_LC7_C10;
-- Node name is '|TONETABA:23|:949'
-- Equation name is '_LC8_C3', type is buried
_LC8_C3 = LCELL( _EQ096);
_EQ096 = _LC1_B8 & !_LC2_B2 & _LC4_B8;
-- Node name is '|TONETABA:23|~950~1'
-- Equation name is '_LC7_C3', type is buried
-- synthesized logic cell
_LC7_C3 = LCELL( _EQ097);
_EQ097 = _LC1_B8 & !_LC2_B2 & !_LC4_B8;
-- Node name is '|TONETABA:23|:958'
-- Equation name is '_LC4_C3', type is buried
_LC4_C3 = LCELL( _EQ098);
_EQ098 = !_LC5_C3 & !_LC6_C3 & _LC8_C3
# !_LC5_C3 & !_LC6_C3 & _LC7_C3;
-- Node name is '|TONETABA:23|:985'
-- Equation name is '_LC2_C5', type is buried
_LC2_C5 = LCELL( _EQ099);
_EQ099 = !_LC2_B2 & _LC3_B8;
Project Information d:\edaplay\digital\test19\rs232\rs232.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,823K
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