count.vhd

几个VHDL实现的源程序及其代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity count is
port(
clk : in std_logic;
clr : in std_logic;
da : buffer std_logic_vector(9 downto 0);
clkout : out std_logic);
end count;

architecture behav of count is
signal carry_out:std_logic;
begin
carry_out<='1' when (da="1001110000") else '0';  --624;
process(clk,clr)
begin
if clr='0' then
da<="1001110000";
elsif clk'event and clk='1' then
if da=624 then
   da<="0000000000";
else
   da<=da+1;
end if;
end if;
end process;

delayclkout:process(carry_out)
variable count:std_logic;
begin
if carry_out'event and carry_out='1' then
     count:=not count;
    if count='1' then clkout<='1';
    else clkout<='0';
    end if;
end if;end process;
end behav;