sc.vhd

几个VHDL实现的源程序及其代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sc is 
  port(clk,rxd:in std_logic;
       data:out std_logic_vector(7 downto 0));
  end sc;

architecture rt8251 of sc is 
  signal count:std_logic_vector(3 downto 0):="0000";
  signal do_latch:std_logic_vector(7 downto 0);
  signal d_fb:std_logic_vector(9 downto 0);
  signal rxdf:std_logic; 
  signal rdfull:std_logic:='0';
begin 
data<=do_latch;

P1:process(clk)
 begin
if(clk'event and clk='1') then
   if ((rxdf='1') and (count="1000") ) then
   do_latch(7 downto 0)<=d_fb(7 downto 0);
   rdfull<='1';
   end if;
end if;
end process p1;

p2:process(clk)
begin
if(clk'event and clk='1')  then
  if(rxd='0')then
    rxdf<='1';
  elsif((rxdf='1') and (count="1000") ) then
     rxdf<='0';
  end if;
end if;
end process p2;

p3:process(clk)
   variable scir:integer range 0 to 8;
   variable scis:std_logic_vector(3 downto 0);
  begin
  if (clk'event and clk='1') then
       if (rxdf='1') then 
           scir:=scir+1;     
       else
          scir:=0;

       end if;
   end if;
   scis:=conv_std_logic_vector(scir,4);
   count<= scis;  
 end process p3;

p4: process(clk)
 begin 
  case count is 
   when "0000"=> d_fb(0)<=rxd;
   when "0001"=> d_fb(1)<=rxd;
   when "0010"=> d_fb(2)<=rxd;
   when "0011"=> d_fb(3)<=rxd;
   when "0100"=> d_fb(4)<=rxd;
   when "0101"=> d_fb(5)<=rxd;
   when "0110"=> d_fb(6)<=rxd;
   when "0111"=> d_fb(7)<=rxd;
   when "1000"=> d_fb(8)<=rxd;
   when others=> d_fb(9)<='1';
   end case;
end process p4;
end rt8251;