dianzhen.rpt

几个VHDL实现的源程序及其代码

         #  _LC2_C14 &  _LC4_C2 & !_LC6_C2;

-- Node name is '|74161:32|f74161:sub|:110' = '|74161:32|f74161:sub|QD' 
-- Equation name is '_LC7_C2', type is buried 
_LC7_C2  = DFFE( _EQ003, GLOBAL( clk),  _LC1_C12,  VCC,  VCC);
  _EQ003 = !_LC6_C2 &  _LC7_C2
         # !_LC2_C14 &  _LC7_C2
         # !_LC4_C2 &  _LC7_C2
         #  _LC2_C14 &  _LC4_C2 &  _LC6_C2 & !_LC7_C2;

-- Node name is '|74161:32|f74161:sub|:104' 
-- Equation name is '_LC3_C2', type is buried 
_LC3_C2  = LCELL( _EQ004);
  _EQ004 =  _LC2_C14 &  _LC4_C2 &  _LC6_C2 &  _LC7_C2;

-- Node name is '|74161:33|f74161:sub|:9' = '|74161:33|f74161:sub|QA' 
-- Equation name is '_LC5_C2', type is buried 
_LC5_C2  = DFFE( _EQ005, GLOBAL( clk),  _LC1_C12,  VCC,  VCC);
  _EQ005 = !_LC3_C2 &  _LC5_C2
         #  _LC3_C2 & !_LC5_C2;

-- Node name is '|74161:33|f74161:sub|:87' = '|74161:33|f74161:sub|QB' 
-- Equation name is '_LC8_C2', type is buried 
_LC8_C2  = DFFE( _EQ006, GLOBAL( clk),  _LC1_C12,  VCC,  VCC);
  _EQ006 = !_LC5_C2 &  _LC8_C2
         # !_LC3_C2 &  _LC8_C2
         #  _LC3_C2 &  _LC5_C2 & !_LC8_C2;

-- Node name is '|74161:33|f74161:sub|:99' = '|74161:33|f74161:sub|QC' 
-- Equation name is '_LC2_C2', type is buried 
_LC2_C2  = DFFE( _EQ007, GLOBAL( clk),  _LC1_C12,  VCC,  VCC);
  _EQ007 = !_LC1_C2 &  _LC2_C2
         #  _LC2_C2 & !_LC3_C2
         #  _LC1_C2 & !_LC2_C2 &  _LC3_C2;

-- Node name is '|74161:33|f74161:sub|:110' = '|74161:33|f74161:sub|QD' 
-- Equation name is '_LC2_C10', type is buried 
_LC2_C10 = DFFE( _EQ008, GLOBAL( clk),  _LC1_C12,  VCC,  VCC);
  _EQ008 = !_LC2_C2 &  _LC2_C10
         # !_LC1_C2 &  _LC2_C10
         #  _LC2_C10 & !_LC3_C2
         #  _LC1_C2 &  _LC2_C2 & !_LC2_C10 &  _LC3_C2;

-- Node name is '|74161:33|f74161:sub|:84' 
-- Equation name is '_LC1_C2', type is buried 
_LC1_C2  = LCELL( _EQ009);
  _EQ009 =  _LC3_C2 &  _LC5_C2 &  _LC8_C2;

-- Node name is '|74161:33|f74161:sub|:104' 
-- Equation name is '_LC3_C10', type is buried 
_LC3_C10 = LCELL( _EQ010);
  _EQ010 =  _LC1_C2 &  _LC2_C2 &  _LC2_C10;

-- Node name is '|74161:70|f74161:sub|:9' = '|74161:70|f74161:sub|QA' 
-- Equation name is '_LC5_C12', type is buried 
_LC5_C12 = DFFE( _EQ011, GLOBAL( clk),  _LC1_C12,  VCC,  VCC);
  _EQ011 = !_LC1_C10 &  _LC5_C12
         #  _LC1_C10 & !_LC5_C12;

-- Node name is '|74161:70|f74161:sub|:87' = '|74161:70|f74161:sub|QB' 
-- Equation name is '_LC6_C12', type is buried 
_LC6_C12 = DFFE( _EQ012, GLOBAL( clk),  _LC1_C12,  VCC,  VCC);
  _EQ012 = !_LC5_C12 &  _LC6_C12
         # !_LC1_C10 &  _LC6_C12
         #  _LC1_C10 &  _LC5_C12 & !_LC6_C12;

-- Node name is '|74161:70|f74161:sub|:99' = '|74161:70|f74161:sub|QC' 
-- Equation name is '_LC8_C12', type is buried 
_LC8_C12 = DFFE( _EQ013, GLOBAL( clk),  _LC1_C12,  VCC,  VCC);
  _EQ013 = !_LC6_C12 &  _LC8_C12
         # !_LC5_C12 &  _LC8_C12
         # !_LC1_C10 &  _LC8_C12
         #  _LC1_C10 &  _LC5_C12 &  _LC6_C12 & !_LC8_C12;

-- Node name is '|74161:70|f74161:sub|:110' = '|74161:70|f74161:sub|QD' 
-- Equation name is '_LC4_C12', type is buried 
_LC4_C12 = DFFE( _EQ014, GLOBAL( clk),  _LC1_C12,  VCC,  VCC);
  _EQ014 =  _LC4_C12 & !_LC6_C12
         #  _LC4_C12 & !_LC7_C12
         #  _LC4_C12 & !_LC8_C12
         # !_LC4_C12 &  _LC6_C12 &  _LC7_C12 &  _LC8_C12;

-- Node name is '|74161:70|f74161:sub|~96~1' 
-- Equation name is '_LC7_C12', type is buried 
-- synthesized logic cell 
_LC7_C12 = LCELL( _EQ015);
  _EQ015 =  _LC1_C10 &  _LC5_C12;

-- Node name is '|74161:83|f74161:sub|:9' = '|74161:83|f74161:sub|QA' 
-- Equation name is '_LC4_C10', type is buried 
_LC4_C10 = DFFE( _EQ016, GLOBAL( clk),  _LC1_C12,  VCC,  VCC);
  _EQ016 = !_LC3_C10 &  _LC4_C10
         #  _LC3_C10 & !_LC4_C10;

-- Node name is '|74161:83|f74161:sub|:87' = '|74161:83|f74161:sub|QB' 
-- Equation name is '_LC5_C10', type is buried 
_LC5_C10 = DFFE( _EQ017, GLOBAL( clk),  _LC1_C12,  VCC,  VCC);
  _EQ017 = !_LC4_C10 &  _LC5_C10
         # !_LC3_C10 &  _LC5_C10
         #  _LC3_C10 &  _LC4_C10 & !_LC5_C10;

-- Node name is '|74161:83|f74161:sub|:99' = '|74161:83|f74161:sub|QC' 
-- Equation name is '_LC7_C10', type is buried 
_LC7_C10 = DFFE( _EQ018, GLOBAL( clk),  _LC1_C12,  VCC,  VCC);
  _EQ018 = !_LC6_C10 &  _LC7_C10
         # !_LC3_C10 &  _LC7_C10
         #  _LC3_C10 &  _LC6_C10 & !_LC7_C10;

-- Node name is '|74161:83|f74161:sub|:110' = '|74161:83|f74161:sub|QD' 
-- Equation name is '_LC8_C10', type is buried 
_LC8_C10 = DFFE( _EQ019, GLOBAL( clk),  _LC1_C12,  VCC,  VCC);
  _EQ019 = !_LC7_C10 &  _LC8_C10
         # !_LC6_C10 &  _LC8_C10
         # !_LC3_C10 &  _LC8_C10
         #  _LC3_C10 &  _LC6_C10 &  _LC7_C10 & !_LC8_C10;

-- Node name is '|74161:83|f74161:sub|:84' 
-- Equation name is '_LC6_C10', type is buried 
_LC6_C10 = LCELL( _EQ020);
  _EQ020 =  _LC3_C10 &  _LC4_C10 &  _LC5_C10;

-- Node name is '|74161:83|f74161:sub|:104' 
-- Equation name is '_LC1_C10', type is buried 
_LC1_C10 = LCELL( _EQ021);
  _EQ021 =  _LC6_C10 &  _LC7_C10 &  _LC8_C10;

-- Node name is '|74373:55|:12' 
-- Equation name is '_LC1_C22', type is buried 
_LC1_C22 = LCELL( _LC4_C2);

-- Node name is '|74373:55|:13' 
-- Equation name is '_LC7_C5', type is buried 
_LC7_C5  = LCELL( _LC6_C2);

-- Node name is '|74373:55|:14' 
-- Equation name is '_LC5_C3', type is buried 
_LC5_C3  = LCELL( _LC7_C2);

-- Node name is '|74373:55|:15' 
-- Equation name is '_LC4_C4', type is buried 
_LC4_C4  = LCELL( _LC5_C2);

-- Node name is '|74373:55|:16' 
-- Equation name is '_LC1_C14', type is buried 
_LC1_C14 = LCELL( _LC2_C14);

-- Node name is '|74373:55|:17' 
-- Equation name is '_LC2_C12', type is buried 
_LC2_C12 = LCELL( _LC6_C12);

-- Node name is '|74373:55|:18' 
-- Equation name is '_LC3_C12', type is buried 
_LC3_C12 = LCELL( _LC8_C12);

-- Node name is '|74373:55|:19' 
-- Equation name is '_LC2_C11', type is buried 
_LC2_C11 = LCELL( _LC4_C12);

-- Node name is ':82' 
-- Equation name is '_LC1_C12', type is buried 
_LC1_C12 = LCELL( _EQ022);
  _EQ022 = !_LC6_C12
         # !_LC4_C12
         # !_LC8_C12;

-- Node name is '|LPM_ROM:1|altrom:srom|segment0_0' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC4_C', type is memory 
_EC4_C   = MEMORY_SEGMENT( VCC, VCC, VCC, GND, VCC, _LC1_C14, _LC1_C22, _LC7_C5, _LC5_C3, _LC4_C4, _LC2_C12, _LC3_C12, _LC2_C11, VCC, VCC, VCC,);

-- Node name is '|LPM_ROM:1|altrom:srom|segment0_1' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC6_C', type is memory 
_EC6_C   = MEMORY_SEGMENT( VCC, VCC, VCC, GND, VCC, _LC1_C14, _LC1_C22, _LC7_C5, _LC5_C3, _LC4_C4, _LC2_C12, _LC3_C12, _LC2_C11, VCC, VCC, VCC,);

-- Node name is '|LPM_ROM:1|altrom:srom|segment0_2' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC2_C', type is memory 
_EC2_C   = MEMORY_SEGMENT( VCC, VCC, VCC, GND, VCC, _LC1_C14, _LC1_C22, _LC7_C5, _LC5_C3, _LC4_C4, _LC2_C12, _LC3_C12, _LC2_C11, VCC, VCC, VCC,);

-- Node name is '|LPM_ROM:1|altrom:srom|segment0_3' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC5_C', type is memory 
_EC5_C   = MEMORY_SEGMENT( VCC, VCC, VCC, GND, VCC, _LC1_C14, _LC1_C22, _LC7_C5, _LC5_C3, _LC4_C4, _LC2_C12, _LC3_C12, _LC2_C11, VCC, VCC, VCC,);

-- Node name is '|LPM_ROM:1|altrom:srom|segment0_4' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC7_C', type is memory 
_EC7_C   = MEMORY_SEGMENT( VCC, VCC, VCC, GND, VCC, _LC1_C14, _LC1_C22, _LC7_C5, _LC5_C3, _LC4_C4, _LC2_C12, _LC3_C12, _LC2_C11, VCC, VCC, VCC,);

-- Node name is '|LPM_ROM:1|altrom:srom|segment0_5' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC8_C', type is memory 
_EC8_C   = MEMORY_SEGMENT( VCC, VCC, VCC, GND, VCC, _LC1_C14, _LC1_C22, _LC7_C5, _LC5_C3, _LC4_C4, _LC2_C12, _LC3_C12, _LC2_C11, VCC, VCC, VCC,);

-- Node name is '|LPM_ROM:1|altrom:srom|segment0_6' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC3_C', type is memory 
_EC3_C   = MEMORY_SEGMENT( VCC, VCC, VCC, GND, VCC, _LC1_C14, _LC1_C22, _LC7_C5, _LC5_C3, _LC4_C4, _LC2_C12, _LC3_C12, _LC2_C11, VCC, VCC, VCC,);

-- Node name is '|LPM_ROM:1|altrom:srom|segment0_7' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC1_C', type is memory 
_EC1_C   = MEMORY_SEGMENT( VCC, VCC, VCC, GND, VCC, _LC1_C14, _LC1_C22, _LC7_C5, _LC5_C3, _LC4_C4, _LC2_C12, _LC3_C12, _LC2_C11, VCC, VCC, VCC,);



Project Information c:\windows\desktop\edaprogramm\digital\test17\dianzhen.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 12,705K