📄 dianzhen.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:c:\windows\desktop\edaprogramm\digital\test17\dianzhen.rpt
dianzhen
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
54 - - - 21 OUTPUT 0 1 0 0 a2
58 - - C -- OUTPUT 0 1 0 0 a3
59 - - C -- OUTPUT 0 1 0 0 a4
60 - - C -- OUTPUT 0 1 0 0 a5
66 - - B -- OUTPUT 0 1 0 0 d0
67 - - B -- OUTPUT 0 1 0 0 d1
70 - - A -- OUTPUT 0 1 0 0 d2
71 - - A -- OUTPUT 0 1 0 0 d3
72 - - A -- OUTPUT 0 1 0 0 d4
73 - - A -- OUTPUT 0 1 0 0 d5
78 - - - 24 OUTPUT 0 1 0 0 d6
79 - - - 24 OUTPUT 0 1 0 0 d7
47 - - - 14 OUTPUT 0 1 0 0 sel
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:c:\windows\desktop\edaprogramm\digital\test17\dianzhen.rpt
dianzhen
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - B 20 SOFT s r 0 1 1 0 d0~fit~in1
- 1 - C 11 SOFT s r 0 1 1 0 d1~fit~in1
- 5 - C 21 SOFT s r 0 1 1 0 d2~fit~in1
- 4 - C 24 SOFT s r 0 1 1 0 d3~fit~in1
- 3 - C 15 SOFT s r 0 1 1 0 d4~fit~in1
- 1 - A 16 SOFT s r 0 1 1 0 d5~fit~in1
- 1 - C 23 SOFT s r 0 1 1 0 d6~fit~in1
- 2 - C 23 SOFT s r 0 1 1 0 d7~fit~in1
- - 4 C -- MEM_SGMT 0 8 0 1 |LPM_ROM:1|altrom:srom|segment0_0
- - 6 C -- MEM_SGMT 0 8 0 1 |LPM_ROM:1|altrom:srom|segment0_1
- - 2 C -- MEM_SGMT 0 8 0 1 |LPM_ROM:1|altrom:srom|segment0_2
- - 5 C -- MEM_SGMT 0 8 0 1 |LPM_ROM:1|altrom:srom|segment0_3
- - 7 C -- MEM_SGMT 0 8 0 1 |LPM_ROM:1|altrom:srom|segment0_4
- - 8 C -- MEM_SGMT 0 8 0 1 |LPM_ROM:1|altrom:srom|segment0_5
- - 3 C -- MEM_SGMT 0 8 0 1 |LPM_ROM:1|altrom:srom|segment0_6
- - 1 C -- MEM_SGMT 0 8 0 1 |LPM_ROM:1|altrom:srom|segment0_7
- 1 - C 12 OR2 0 3 0 16 :82
- 2 - C 14 DFFE + 0 1 1 5 |74161:32|f74161:sub|QA (|74161:32|f74161:sub|:9)
- 4 - C 02 DFFE + 0 2 0 4 |74161:32|f74161:sub|QB (|74161:32|f74161:sub|:87)
- 6 - C 02 DFFE + 0 3 0 3 |74161:32|f74161:sub|QC (|74161:32|f74161:sub|:99)
- 3 - C 02 AND2 0 4 0 5 |74161:32|f74161:sub|:104
- 7 - C 02 DFFE + 0 4 0 2 |74161:32|f74161:sub|QD (|74161:32|f74161:sub|:110)
- 5 - C 02 DFFE + 0 2 0 3 |74161:33|f74161:sub|QA (|74161:33|f74161:sub|:9)
- 1 - C 02 AND2 0 3 0 3 |74161:33|f74161:sub|:84
- 8 - C 02 DFFE + 0 3 0 1 |74161:33|f74161:sub|QB (|74161:33|f74161:sub|:87)
- 2 - C 02 DFFE + 0 3 0 2 |74161:33|f74161:sub|QC (|74161:33|f74161:sub|:99)
- 3 - C 10 AND2 0 3 0 5 |74161:33|f74161:sub|:104
- 2 - C 10 DFFE + 0 4 0 1 |74161:33|f74161:sub|QD (|74161:33|f74161:sub|:110)
- 5 - C 12 DFFE + 0 2 0 3 |74161:70|f74161:sub|QA (|74161:70|f74161:sub|:9)
- 6 - C 12 DFFE + 0 3 0 4 |74161:70|f74161:sub|QB (|74161:70|f74161:sub|:87)
- 7 - C 12 AND2 s 0 2 0 1 |74161:70|f74161:sub|~96~1
- 8 - C 12 DFFE + 0 4 0 3 |74161:70|f74161:sub|QC (|74161:70|f74161:sub|:99)
- 4 - C 12 DFFE + 0 4 0 2 |74161:70|f74161:sub|QD (|74161:70|f74161:sub|:110)
- 4 - C 10 DFFE + 0 2 0 2 |74161:83|f74161:sub|QA (|74161:83|f74161:sub|:9)
- 6 - C 10 AND2 0 3 0 3 |74161:83|f74161:sub|:84
- 5 - C 10 DFFE + 0 3 0 1 |74161:83|f74161:sub|QB (|74161:83|f74161:sub|:87)
- 7 - C 10 DFFE + 0 3 0 2 |74161:83|f74161:sub|QC (|74161:83|f74161:sub|:99)
- 1 - C 10 AND2 0 3 0 4 |74161:83|f74161:sub|:104
- 8 - C 10 DFFE + 0 4 0 1 |74161:83|f74161:sub|QD (|74161:83|f74161:sub|:110)
- 1 - C 22 LCELL 0 1 1 8 |74373:55|:12
- 7 - C 05 LCELL 0 1 1 8 |74373:55|:13
- 5 - C 03 LCELL 0 1 1 8 |74373:55|:14
- 4 - C 04 LCELL 0 1 1 8 |74373:55|:15
- 1 - C 14 LCELL 0 1 0 8 |74373:55|:16
- 2 - C 12 LCELL 0 1 0 8 |74373:55|:17
- 3 - C 12 LCELL 0 1 0 8 |74373:55|:18
- 2 - C 11 LCELL 0 1 0 8 |74373:55|:19
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:c:\windows\desktop\edaprogramm\digital\test17\dianzhen.rpt
dianzhen
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 4/ 48( 8%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 2/ 96( 2%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 14/ 96( 14%) 12/ 48( 25%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:c:\windows\desktop\edaprogramm\digital\test17\dianzhen.rpt
dianzhen
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 clk
Device-Specific Information:c:\windows\desktop\edaprogramm\digital\test17\dianzhen.rpt
dianzhen
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 16 :82
Device-Specific Information:c:\windows\desktop\edaprogramm\digital\test17\dianzhen.rpt
dianzhen
** EQUATIONS **
clk : INPUT;
-- Node name is 'a2'
-- Equation name is 'a2', type is output
a2 = _LC1_C22;
-- Node name is 'a3'
-- Equation name is 'a3', type is output
a3 = _LC7_C5;
-- Node name is 'a4'
-- Equation name is 'a4', type is output
a4 = _LC5_C3;
-- Node name is 'a5'
-- Equation name is 'a5', type is output
a5 = _LC4_C4;
-- Node name is 'd0~fit~in1'
-- Equation name is 'd0~fit~in1', location is LC2_B20, type is buried.
-- synthesized logic cell
_LC2_B20 = LCELL( _EC4_C);
-- Node name is 'd0'
-- Equation name is 'd0', type is output
d0 = _LC2_B20;
-- Node name is 'd1~fit~in1'
-- Equation name is 'd1~fit~in1', location is LC1_C11, type is buried.
-- synthesized logic cell
_LC1_C11 = LCELL( _EC6_C);
-- Node name is 'd1'
-- Equation name is 'd1', type is output
d1 = _LC1_C11;
-- Node name is 'd2~fit~in1'
-- Equation name is 'd2~fit~in1', location is LC5_C21, type is buried.
-- synthesized logic cell
_LC5_C21 = LCELL( _EC2_C);
-- Node name is 'd2'
-- Equation name is 'd2', type is output
d2 = _LC5_C21;
-- Node name is 'd3~fit~in1'
-- Equation name is 'd3~fit~in1', location is LC4_C24, type is buried.
-- synthesized logic cell
_LC4_C24 = LCELL( _EC5_C);
-- Node name is 'd3'
-- Equation name is 'd3', type is output
d3 = _LC4_C24;
-- Node name is 'd4~fit~in1'
-- Equation name is 'd4~fit~in1', location is LC3_C15, type is buried.
-- synthesized logic cell
_LC3_C15 = LCELL( _EC7_C);
-- Node name is 'd4'
-- Equation name is 'd4', type is output
d4 = _LC3_C15;
-- Node name is 'd5~fit~in1'
-- Equation name is 'd5~fit~in1', location is LC1_A16, type is buried.
-- synthesized logic cell
_LC1_A16 = LCELL( _EC8_C);
-- Node name is 'd5'
-- Equation name is 'd5', type is output
d5 = _LC1_A16;
-- Node name is 'd6~fit~in1'
-- Equation name is 'd6~fit~in1', location is LC1_C23, type is buried.
-- synthesized logic cell
_LC1_C23 = LCELL( _EC3_C);
-- Node name is 'd6'
-- Equation name is 'd6', type is output
d6 = _LC1_C23;
-- Node name is 'd7~fit~in1'
-- Equation name is 'd7~fit~in1', location is LC2_C23, type is buried.
-- synthesized logic cell
_LC2_C23 = LCELL( _EC1_C);
-- Node name is 'd7'
-- Equation name is 'd7', type is output
d7 = _LC2_C23;
-- Node name is 'sel'
-- Equation name is 'sel', type is output
sel = _LC2_C14;
-- Node name is '|74161:32|f74161:sub|:9' = '|74161:32|f74161:sub|QA'
-- Equation name is '_LC2_C14', type is buried
_LC2_C14 = DFFE(!_LC2_C14, GLOBAL( clk), _LC1_C12, VCC, VCC);
-- Node name is '|74161:32|f74161:sub|:87' = '|74161:32|f74161:sub|QB'
-- Equation name is '_LC4_C2', type is buried
_LC4_C2 = DFFE( _EQ001, GLOBAL( clk), _LC1_C12, VCC, VCC);
_EQ001 = _LC2_C14 & !_LC4_C2
# !_LC2_C14 & _LC4_C2;
-- Node name is '|74161:32|f74161:sub|:99' = '|74161:32|f74161:sub|QC'
-- Equation name is '_LC6_C2', type is buried
_LC6_C2 = DFFE( _EQ002, GLOBAL( clk), _LC1_C12, VCC, VCC);
_EQ002 = !_LC2_C14 & _LC6_C2
# !_LC4_C2 & _LC6_C2
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