📄 display2.rpt
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_EQ006 = !_LC3_A10 & !_LC4_A5 & _LC4_A10 & !_LC6_A10
# _LC3_A10 & !_LC4_A5 & !_LC4_A10 & _LC6_A10;
-- Node name is '|deled:11|~153~2' from file "deled.tdf" line 17, column 24
-- Equation name is '_LC8_A8', type is buried
-- synthesized logic cell
_LC8_A8 = LCELL( _EQ007);
_EQ007 = !_LC3_A10 & !_LC4_A5 & !_LC4_A10 & _LC6_A10
# _LC3_A10 & _LC4_A5 & !_LC4_A10 & _LC6_A10
# !_LC3_A10 & _LC4_A5 & !_LC4_A10 & !_LC6_A10
# _LC3_A10 & !_LC4_A5 & !_LC4_A10 & !_LC6_A10;
-- Node name is '|deled:11|~155~1' from file "deled.tdf" line 17, column 26
-- Equation name is '_LC5_A10', type is buried
-- synthesized logic cell
_LC5_A10 = LCELL( _EQ008);
_EQ008 = !_LC3_A10 & _LC4_A5 & !_LC4_A10
# _LC3_A10 & !_LC4_A5 & !_LC4_A10 & !_LC6_A10;
-- Node name is '|deled:11|:157' from file "deled.tdf" line 17, column 28
-- Equation name is '_LC3_A8', type is buried
_LC3_A8 = LCELL( _EQ009);
_EQ009 = _LC3_A10 & _LC4_A5 & !_LC4_A10
# _LC4_A5 & !_LC4_A10 & !_LC6_A10
# !_LC3_A10 & !_LC4_A10 & _LC6_A10
# _LC3_A10 & !_LC4_A10 & !_LC6_A10
# !_LC3_A10 & !_LC4_A5 & !_LC6_A10
# !_LC3_A10 & !_LC4_A5 & !_LC4_A10;
-- Node name is '|SELTIME:12|:24' = '|SELTIME:12|sec0'
-- Equation name is '_LC5_A4', type is buried
_LC5_A4 = DFFE(!_LC5_A4, GLOBAL( CKDSP), clr, VCC, VCC);
-- Node name is '|SELTIME:12|:23' = '|SELTIME:12|sec1'
-- Equation name is '_LC7_A4', type is buried
_LC7_A4 = DFFE( _EQ010, GLOBAL( CKDSP), clr, VCC, VCC);
_EQ010 = _LC5_A4 & !_LC6_A4 & !_LC7_A4
# !_LC5_A4 & !_LC6_A4 & _LC7_A4;
-- Node name is '|SELTIME:12|:22' = '|SELTIME:12|sec2'
-- Equation name is '_LC2_A4', type is buried
_LC2_A4 = DFFE( _EQ011, GLOBAL( CKDSP), clr, VCC, VCC);
_EQ011 = _LC2_A4 & !_LC5_A4 & !_LC6_A4
# _LC2_A4 & !_LC6_A4 & !_LC7_A4
# !_LC2_A4 & _LC5_A4 & !_LC6_A4 & _LC7_A4;
-- Node name is '|SELTIME:12|:51'
-- Equation name is '_LC6_A4', type is buried
!_LC6_A4 = _LC6_A4~NOT;
_LC6_A4~NOT = LCELL( _EQ012);
_EQ012 = _LC2_A4
# !_LC5_A4
# !_LC7_A4;
-- Node name is '|SELTIME:12|:384'
-- Equation name is '_LC3_A4', type is buried
_LC3_A4 = LCELL( _EQ013);
_EQ013 = !_LC2_A4 & !_LC5_A4 & _LC7_A4;
-- Node name is '|SELTIME:12|:394'
-- Equation name is '_LC8_A4', type is buried
_LC8_A4 = LCELL( _EQ014);
_EQ014 = !_LC2_A4 & _LC5_A4 & !_LC7_A4;
-- Node name is '|SELTIME:12|:404'
-- Equation name is '_LC2_A5', type is buried
_LC2_A5 = LCELL( _EQ015);
_EQ015 = !_LC2_A4 & !_LC5_A4 & !_LC7_A4;
-- Node name is '|SELTIME:12|:422'
-- Equation name is '_LC6_A5', type is buried
_LC6_A5 = LCELL( _EQ016);
_EQ016 = !_LC2_A4 & _LC3_A5;
-- Node name is '|SELTIME:12|:437'
-- Equation name is '_LC4_A4', type is buried
_LC4_A4 = LCELL( _EQ017);
_EQ017 = !_LC2_A4 & _LC3_A8;
-- Node name is '|SELTIME:12|:452'
-- Equation name is '_LC1_A10', type is buried
_LC1_A10 = LCELL( _EQ018);
_EQ018 = _LC1_A5 & !_LC8_A10
# _LC1_A5 & _LC2_A8
# _LC1_A5 & _LC5_A10;
-- Node name is '|SELTIME:12|:467'
-- Equation name is '_LC1_A8', type is buried
_LC1_A8 = LCELL( _EQ019);
_EQ019 = _LC1_A5 & _LC8_A8
# _LC1_A5 & _LC4_A8;
-- Node name is '|SELTIME:12|:482'
-- Equation name is '_LC6_A8', type is buried
_LC6_A8 = LCELL( _EQ020);
_EQ020 = _LC1_A5 & _LC2_A8;
-- Node name is '|SELTIME:12|:497'
-- Equation name is '_LC5_A8', type is buried
_LC5_A8 = LCELL( _EQ021);
_EQ021 = _LC1_A5 & _LC4_A8
# _LC1_A5 & _LC7_A8;
-- Node name is '|SELTIME:12|~512~1'
-- Equation name is '_LC1_A5', type is buried
-- synthesized logic cell
_LC1_A5 = LCELL(!_LC2_A4);
-- Node name is '|SELTIME:12|:512'
-- Equation name is '_LC2_A10', type is buried
_LC2_A10 = LCELL( _EQ022);
_EQ022 = _LC1_A5 & _LC5_A10
# _LC1_A5 & _LC7_A10;
-- Node name is '|74138:15|:19' = '|74138:15|Y4N'
-- Equation name is '_LC2_A2', type is buried
!_LC2_A2 = _LC2_A2~NOT;
_LC2_A2~NOT = LCELL( _EQ023);
_EQ023 = _LC2_A4 & !_LC5_A4 & !_LC7_A4;
-- Node name is '|74138:15|:20' = '|74138:15|Y5N'
-- Equation name is '_LC1_A2', type is buried
!_LC1_A2 = _LC1_A2~NOT;
_LC1_A2~NOT = LCELL( _EQ024);
_EQ024 = _LC2_A4 & _LC5_A4 & !_LC7_A4;
-- Node name is '|74138:15|:21' = '|74138:15|Y6N'
-- Equation name is '_LC4_A2', type is buried
!_LC4_A2 = _LC4_A2~NOT;
_LC4_A2~NOT = LCELL( _EQ025);
_EQ025 = _LC2_A4 & !_LC5_A4 & _LC7_A4;
-- Node name is '|74138:15|:22' = '|74138:15|Y7N'
-- Equation name is '_LC1_A4', type is buried
!_LC1_A4 = _LC1_A4~NOT;
_LC1_A4~NOT = LCELL( _EQ026);
_EQ026 = _LC2_A4 & _LC5_A4 & _LC7_A4;
-- Node name is '|74161:1|f74161:sub|:9' = '|74161:1|f74161:sub|QA'
-- Equation name is '_LC6_A10', type is buried
_LC6_A10 = DFFE( _EQ027, GLOBAL( clk), clr, VCC, VCC);
_EQ027 = _LC3_A10 & !_LC6_A10
# !_LC4_A10 & !_LC6_A10
# _LC4_A5 & !_LC6_A10;
-- Node name is '|74161:1|f74161:sub|:87' = '|74161:1|f74161:sub|QB'
-- Equation name is '_LC3_A10', type is buried
_LC3_A10 = DFFE( _EQ028, GLOBAL( clk), clr, VCC, VCC);
_EQ028 = !_LC3_A10 & _LC6_A10
# _LC3_A10 & !_LC6_A10;
-- Node name is '|74161:1|f74161:sub|:99' = '|74161:1|f74161:sub|QC'
-- Equation name is '_LC4_A5', type is buried
_LC4_A5 = DFFE( _EQ029, GLOBAL( clk), clr, VCC, VCC);
_EQ029 = _LC4_A5 & !_LC6_A10
# !_LC3_A10 & _LC4_A5
# _LC3_A10 & !_LC4_A5 & _LC6_A10;
-- Node name is '|74161:1|f74161:sub|:110' = '|74161:1|f74161:sub|QD'
-- Equation name is '_LC4_A10', type is buried
_LC4_A10 = DFFE( _EQ030, GLOBAL( clk), clr, VCC, VCC);
_EQ030 = _LC3_A10 & _LC4_A5 & !_LC4_A10 & _LC6_A10
# !_LC3_A10 & _LC4_A10 & _LC6_A10
# !_LC4_A5 & _LC4_A10 & _LC6_A10
# _LC3_A10 & _LC4_A10 & !_LC6_A10
# _LC3_A10 & !_LC4_A5 & _LC4_A10
# _LC4_A5 & _LC4_A10 & !_LC6_A10
# !_LC3_A10 & _LC4_A5 & _LC4_A10;
Project Information d:\edaplay\digital\test4\display2\display2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,832K
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