📄 display2.rpt
字号:
display2
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
17 - - A -- OUTPUT 0 1 0 0 Q0
18 - - A -- OUTPUT 0 1 0 0 Q1
19 - - A -- OUTPUT 0 1 0 0 Q2
21 - - B -- OUTPUT 0 1 0 0 Q3
22 - - B -- OUTPUT 0 1 0 0 Q4
23 - - B -- OUTPUT 0 1 0 0 Q5
24 - - B -- OUTPUT 0 1 0 0 Q6
25 - - B -- OUTPUT 0 0 0 0 Q7
5 - - - 05 OUTPUT 0 1 0 0 Y0
6 - - - 04 OUTPUT 0 1 0 0 Y1
7 - - - 03 OUTPUT 0 1 0 0 Y2
8 - - - 03 OUTPUT 0 1 0 0 Y3
9 - - - 02 OUTPUT 0 1 0 0 Y4
10 - - - 01 OUTPUT 0 1 0 0 Y5
11 - - - 01 OUTPUT 0 1 0 0 Y6
16 - - A -- OUTPUT 0 1 0 0 Y7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\edaplay\digital\test4\display2\display2.rpt
display2
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - A 05 OR2 0 4 0 1 |deled:11|:129
- 8 - A 10 AND2 ! 0 4 0 1 |deled:11|:135
- 7 - A 10 AND2 s 0 3 0 1 |deled:11|~147~1
- 7 - A 08 OR2 s 0 4 0 1 |deled:11|~149~1
- 2 - A 08 OR2 0 4 0 2 |deled:11|:151
- 4 - A 08 OR2 s 0 4 0 2 |deled:11|~153~1
- 8 - A 08 OR2 s 0 4 0 1 |deled:11|~153~2
- 5 - A 10 OR2 s 0 4 0 2 |deled:11|~155~1
- 3 - A 08 OR2 0 4 0 1 |deled:11|:157
- 2 - A 04 DFFE + 1 3 0 11 |SELTIME:12|sec2 (|SELTIME:12|:22)
- 7 - A 04 DFFE + 1 2 0 9 |SELTIME:12|sec1 (|SELTIME:12|:23)
- 5 - A 04 DFFE + 1 0 0 10 |SELTIME:12|sec0 (|SELTIME:12|:24)
- 6 - A 04 OR2 ! 0 3 1 2 |SELTIME:12|:51
- 3 - A 04 AND2 0 3 1 0 |SELTIME:12|:384
- 8 - A 04 AND2 0 3 1 0 |SELTIME:12|:394
- 2 - A 05 AND2 0 3 1 0 |SELTIME:12|:404
- 6 - A 05 AND2 0 2 1 0 |SELTIME:12|:422
- 4 - A 04 AND2 0 2 1 0 |SELTIME:12|:437
- 1 - A 10 OR2 0 4 1 0 |SELTIME:12|:452
- 1 - A 08 OR2 0 3 1 0 |SELTIME:12|:467
- 6 - A 08 AND2 0 2 1 0 |SELTIME:12|:482
- 5 - A 08 OR2 0 3 1 0 |SELTIME:12|:497
- 1 - A 05 AND2 s 0 1 0 5 |SELTIME:12|~512~1
- 2 - A 10 OR2 0 3 1 0 |SELTIME:12|:512
- 2 - A 02 AND2 ! 0 3 1 0 |74138:15|Y4N (|74138:15|:19)
- 1 - A 02 AND2 ! 0 3 1 0 |74138:15|Y5N (|74138:15|:20)
- 4 - A 02 AND2 ! 0 3 1 0 |74138:15|Y6N (|74138:15|:21)
- 1 - A 04 AND2 ! 0 3 1 0 |74138:15|Y7N (|74138:15|:22)
- 6 - A 10 DFFE + 1 3 0 12 |74161:1|f74161:sub|QA (|74161:1|f74161:sub|:9)
- 3 - A 10 DFFE + 1 1 0 12 |74161:1|f74161:sub|QB (|74161:1|f74161:sub|:87)
- 4 - A 05 DFFE + 1 2 0 11 |74161:1|f74161:sub|QC (|74161:1|f74161:sub|:99)
- 4 - A 10 DFFE + 1 3 0 9 |74161:1|f74161:sub|QD (|74161:1|f74161:sub|:110)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\edaplay\digital\test4\display2\display2.rpt
display2
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 14/ 48( 29%) 0/ 48( 0%) 1/16( 6%) 4/16( 25%) 0/16( 0%)
B: 0/ 96( 0%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\edaplay\digital\test4\display2\display2.rpt
display2
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 clk
INPUT 3 CKDSP
Device-Specific Information: d:\edaplay\digital\test4\display2\display2.rpt
display2
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 7 clr
Device-Specific Information: d:\edaplay\digital\test4\display2\display2.rpt
display2
** EQUATIONS **
CKDSP : INPUT;
clk : INPUT;
clr : INPUT;
-- Node name is 'Q0'
-- Equation name is 'Q0', type is output
Q0 = _LC2_A10;
-- Node name is 'Q1'
-- Equation name is 'Q1', type is output
Q1 = _LC5_A8;
-- Node name is 'Q2'
-- Equation name is 'Q2', type is output
Q2 = _LC6_A8;
-- Node name is 'Q3'
-- Equation name is 'Q3', type is output
Q3 = _LC1_A8;
-- Node name is 'Q4'
-- Equation name is 'Q4', type is output
Q4 = _LC1_A10;
-- Node name is 'Q5'
-- Equation name is 'Q5', type is output
Q5 = _LC4_A4;
-- Node name is 'Q6'
-- Equation name is 'Q6', type is output
Q6 = _LC6_A5;
-- Node name is 'Q7'
-- Equation name is 'Q7', type is output
Q7 = GND;
-- Node name is 'Y0'
-- Equation name is 'Y0', type is output
Y0 = _LC2_A5;
-- Node name is 'Y1'
-- Equation name is 'Y1', type is output
Y1 = _LC8_A4;
-- Node name is 'Y2'
-- Equation name is 'Y2', type is output
Y2 = _LC3_A4;
-- Node name is 'Y3'
-- Equation name is 'Y3', type is output
Y3 = _LC6_A4;
-- Node name is 'Y4'
-- Equation name is 'Y4', type is output
Y4 = !_LC2_A2;
-- Node name is 'Y5'
-- Equation name is 'Y5', type is output
Y5 = !_LC1_A2;
-- Node name is 'Y6'
-- Equation name is 'Y6', type is output
Y6 = !_LC4_A2;
-- Node name is 'Y7'
-- Equation name is 'Y7', type is output
Y7 = !_LC1_A4;
-- Node name is '|deled:11|:129' from file "deled.tdf" line 15, column 30
-- Equation name is '_LC3_A5', type is buried
_LC3_A5 = LCELL( _EQ001);
_EQ001 = !_LC4_A5 & !_LC4_A10 & _LC6_A10
# _LC4_A5 & !_LC4_A10 & !_LC6_A10
# !_LC3_A10 & !_LC4_A10;
-- Node name is '|deled:11|:135' from file "deled.tdf" line 16, column 5
-- Equation name is '_LC8_A10', type is buried
!_LC8_A10 = _LC8_A10~NOT;
_LC8_A10~NOT = LCELL( _EQ002);
_EQ002 = _LC3_A10 & _LC4_A5 & !_LC4_A10 & _LC6_A10;
-- Node name is '|deled:11|~147~1' from file "deled.tdf" line 17, column 18
-- Equation name is '_LC7_A10', type is buried
-- synthesized logic cell
_LC7_A10 = LCELL( _EQ003);
_EQ003 = !_LC3_A10 & !_LC4_A5 & !_LC6_A10;
-- Node name is '|deled:11|~149~1' from file "deled.tdf" line 17, column 20
-- Equation name is '_LC7_A8', type is buried
-- synthesized logic cell
_LC7_A8 = LCELL( _EQ004);
_EQ004 = _LC3_A10 & _LC4_A5 & !_LC4_A10 & !_LC6_A10
# !_LC3_A10 & !_LC4_A5 & !_LC4_A10 & !_LC6_A10;
-- Node name is '|deled:11|:151' from file "deled.tdf" line 17, column 22
-- Equation name is '_LC2_A8', type is buried
_LC2_A8 = LCELL( _EQ005);
_EQ005 = _LC3_A10 & _LC4_A5 & !_LC4_A10 & !_LC6_A10
# !_LC3_A10 & !_LC4_A5 & !_LC4_A10
# !_LC3_A10 & !_LC4_A5 & !_LC6_A10
# !_LC4_A5 & !_LC4_A10 & _LC6_A10;
-- Node name is '|deled:11|~153~1' from file "deled.tdf" line 17, column 24
-- Equation name is '_LC4_A8', type is buried
-- synthesized logic cell
_LC4_A8 = LCELL( _EQ006);
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