kb2pc1.vhd

几个VHDL实现的源程序及其代码

library ieee;
use ieee.std_logic_1164.all;

entity kb2pc1 is
port(
sysclk: in std_logic;
reset: in std_logic;
kbclk: in std_logic;
kbdata: in std_logic;
pdata : out std_logic_vector(7 downto 0);
parity : out std_logic;
dtoe : out std_logic);
end kb2pc1;

architecture one of kb2pc1 is
signal costate: std_logic_vector(1 downto 0);
signal spdata: std_logic_vector(8 downto 0);
signal start,swto02 : std_logic;
signal cnt8: integer range 0 to 15;
begin

str1:process(reset,kbclk,kbdata,start,costate)
begin
if reset='0' then
start<='0';
elsif kbclk'event and kbclk='0' then
if costate="00" and kbdata='0' then
start<='1';
end if;
end if;
end process;

str2:process(reset,kbclk,kbdata,start,costate)
begin
if reset='0' then
swto02<='0';
elsif kbclk'event and kbclk='1' then
if costate="00" and start='1' and kbdata='0' then
swto02<='1';
end if;
end if;
end process;

chstate: process(cnt8,reset,sysclk,costate,swto02)
begin
if reset='0' then
costate<="00";
elsif sysclk'event and sysclk='1' then
if swto02='1' then
costate<="01";
elsif cnt8=9 then
costate<="10";
end if;
end if;
end process;

RECV:PROCESS(cnt8,reset,kbclk,kbdata,costate)
begin
if reset='0' then
cnt8<=0; 
spdata<="000000000";
elsif kbclk'event and kbclk='0' then
if costate="01" then
if cnt8/=9 then
cnt8<=cnt8+1;
spdata(7 downto 0)<=spdata(8 downto 1);
spdata(8)<=kbdata;
end if;
end if;
end if;
end process;

recvend:process(cnt8,reset,kbclk,costate)
begin
if reset='0' then
dtoe<='0';
elsif kbclk'event and kbclk='1' then
if cnt8=9 and costate="01" then
dtoe<='1';
end if;
end if;
end process;
parity<=spdata(8);
pdata<=spdata(7 downto 0);
end one;