seltime.vhd

几个VHDL实现的源程序及其代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity seltime is
port(
     clk : in std_logic;
     rst : in std_logic;
     din : in std_logic_vector(31 downto 0);
     daout: out std_logic_vector(3 downto 0);
     sel : out std_logic_vector(2 downto 0));
end seltime;

architecture behav of seltime is
signal sec : std_logic_vector(2 downto 0);
begin
process(rst,clk)
begin
if(rst='0') then
sec<="000";
elsif(clk'event and clk='1') then  
if(sec="111") then
   sec<="000";
else
   sec<=sec+1;
end if;
end if;
end process;
process(sec,din(31 downto 0))
begin
case sec is
when "000"=>daout<=din(3 downto 0);
when "001"=>daout<=din(7 downto 4);
when "010"=>daout<=din(11 downto 8);
when "011"=>daout<=din(15 downto 12);
when "100"=>daout<=din(19 downto 16);
when "101"=>daout<=din(23 downto 20);
when "110"=>daout<=din(27 downto 24);
when "111"=>daout<=din(31 downto 25);
when others=>daout<="XXXX";
end case;
end process;
sel<=sec;
end behav;