📄 add8.rpt
字号:
10 - - - 01 OUTPUT 0 1 0 0 Y5
11 - - - 01 OUTPUT 0 1 0 0 Y6
16 - - A -- OUTPUT 0 1 0 0 Y7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\edaplay\digital\test7\add8.rpt
add8
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - B 15 OR2 4 0 0 3 |ADD4:1|LPM_ADD_SUB:46|addcore:adder|pcarry1
- 7 - B 15 OR2 2 1 0 2 |ADD4:1|LPM_ADD_SUB:46|addcore:adder|pcarry2
- 6 - B 15 OR2 4 0 0 2 |ADD4:1|LPM_ADD_SUB:46|addcore:adder|:88
- 8 - B 15 OR2 3 1 0 2 |ADD4:1|LPM_ADD_SUB:47|addcore:adder|:59
- 4 - B 15 OR2 2 2 0 2 |ADD4:1|LPM_ADD_SUB:47|addcore:adder|:63
- 1 - B 15 OR2 3 1 0 1 |ADD4:1|LPM_ADD_SUB:47|addcore:adder|:75
- 2 - B 15 OR2 2 2 0 1 |ADD4:1|LPM_ADD_SUB:47|addcore:adder|:76
- 6 - B 13 OR2 2 2 0 1 |ADD4:1|LPM_ADD_SUB:47|addcore:adder|:77
- 5 - B 13 OR2 2 2 0 3 |ADD4:1|LPM_ADD_SUB:47|addcore:adder|:78
- 1 - B 13 OR2 4 0 0 3 |ADD4:2|LPM_ADD_SUB:46|addcore:adder|pcarry1
- 3 - B 23 OR2 2 1 0 2 |ADD4:2|LPM_ADD_SUB:46|addcore:adder|pcarry2
- 4 - B 13 OR2 4 0 0 2 |ADD4:2|LPM_ADD_SUB:46|addcore:adder|:88
- 7 - B 13 OR2 2 2 0 2 |ADD4:2|LPM_ADD_SUB:47|addcore:adder|:59
- 4 - B 23 OR2 2 2 0 2 |ADD4:2|LPM_ADD_SUB:47|addcore:adder|:63
- 8 - B 13 OR2 2 1 0 1 |ADD4:2|LPM_ADD_SUB:47|addcore:adder|:73
- 3 - B 13 OR2 2 2 0 1 |ADD4:2|LPM_ADD_SUB:47|addcore:adder|:75
- 1 - B 23 OR2 2 2 0 1 |ADD4:2|LPM_ADD_SUB:47|addcore:adder|:76
- 8 - B 23 OR2 2 2 0 1 |ADD4:2|LPM_ADD_SUB:47|addcore:adder|:77
- 6 - B 23 OR2 2 2 0 1 |ADD4:2|LPM_ADD_SUB:47|addcore:adder|:78
- 3 - A 13 OR2 ! 0 4 0 2 |DELED:28|:546
- 5 - A 13 AND2 s 0 3 0 1 |DELED:28|~558~1
- 4 - A 13 AND2 0 4 0 2 |DELED:28|:570
- 5 - A 23 OR2 ! 0 4 0 3 |DELED:28|:582
- 4 - A 23 AND2 0 4 0 3 |DELED:28|:594
- 2 - A 23 OR2 s ! 0 2 0 1 |DELED:28|~647~1
- 6 - A 17 OR2 0 4 1 0 |DELED:28|:647
- 4 - A 17 OR2 0 4 1 0 |DELED:28|:693
- 2 - A 17 OR2 0 4 1 0 |DELED:28|:741
- 1 - A 13 OR2 s 0 4 0 1 |DELED:28|~782~1
- 8 - A 23 OR2 0 3 0 1 |DELED:28|:782
- 1 - A 23 OR2 0 4 1 0 |DELED:28|:789
- 6 - A 23 OR2 s 0 4 0 2 |DELED:28|~828~1
- 6 - A 13 OR2 s 0 4 0 1 |DELED:28|~828~2
- 7 - A 13 OR2 0 4 1 0 |DELED:28|:837
- 8 - A 13 OR2 0 4 0 1 |DELED:28|:864
- 5 - A 17 OR2 0 4 1 0 |DELED:28|:885
- 1 - A 17 OR2 0 4 0 1 |DELED:28|:905
- 3 - A 17 OR2 s 0 4 0 1 |DELED:28|~918~1
- 7 - A 23 OR2 0 4 0 1 |DELED:28|:926
- 2 - A 13 OR2 s 0 3 0 2 |DELED:28|~927~1
- 3 - A 23 OR2 0 4 1 0 |DELED:28|:933
- 4 - B 02 DFFE + 0 3 0 8 |SELTIME:26|sec2 (|SELTIME:26|:41)
- 5 - B 02 DFFE + 0 2 0 9 |SELTIME:26|sec1 (|SELTIME:26|:42)
- 1 - B 07 DFFE + 0 0 0 10 |SELTIME:26|sec0 (|SELTIME:26|:43)
- 1 - B 02 OR2 ! 0 3 1 2 |SELTIME:26|:57
- 8 - B 02 OR2 0 4 0 1 |SELTIME:26|:838
- 6 - B 02 OR2 0 4 0 1 |SELTIME:26|:858
- 3 - B 24 OR2 0 3 0 1 |SELTIME:26|:868
- 6 - B 24 OR2 0 3 0 1 |SELTIME:26|:878
- 5 - B 24 OR2 0 3 0 15 |SELTIME:26|:888
- 2 - B 22 OR2 ! 0 4 0 1 |SELTIME:26|:897
- 3 - B 20 OR2 ! 0 4 0 1 |SELTIME:26|:903
- 5 - B 20 OR2 ! 0 3 0 1 |SELTIME:26|:906
- 7 - B 20 OR2 ! 0 3 0 1 |SELTIME:26|:909
- 1 - B 20 OR2 ! 0 3 0 15 |SELTIME:26|:912
- 6 - B 22 OR2 ! 0 4 0 1 |SELTIME:26|:921
- 7 - B 22 OR2 ! 0 4 0 1 |SELTIME:26|:927
- 8 - B 22 OR2 ! 0 3 0 1 |SELTIME:26|:930
- 1 - B 22 OR2 ! 0 3 0 1 |SELTIME:26|:933
- 7 - A 17 OR2 ! 0 3 0 15 |SELTIME:26|:936
- 3 - B 15 OR2 ! 3 1 0 1 |SELTIME:26|:946
- 7 - B 23 OR2 ! 0 4 0 1 |SELTIME:26|:947
- 2 - B 23 OR2 ! 0 4 0 1 |SELTIME:26|:948
- 7 - B 03 OR2 ! 0 3 0 1 |SELTIME:26|:951
- 8 - B 03 OR2 ! 0 3 0 1 |SELTIME:26|:954
- 4 - B 03 OR2 ! 0 3 0 1 |SELTIME:26|:957
- 1 - B 24 OR2 ! 0 3 0 15 |SELTIME:26|:960
- 6 - B 03 LCELL 1 0 0 1 S8 (~56~1)
- 4 - B 22 LCELL 1 0 0 1 S9 (~56~2)
- 4 - B 20 LCELL 1 0 0 1 S10 (~56~3)
- 2 - B 24 LCELL 1 0 0 1 S11 (~56~4)
- 2 - B 13 LCELL 1 0 0 1 S12 (~56~5)
- 5 - B 22 LCELL 1 0 0 1 S13 (~56~6)
- 2 - B 20 LCELL 1 0 0 1 S14 (~56~7)
- 2 - B 19 LCELL 1 0 0 1 S15 (~56~8)
- 8 - B 24 LCELL 1 0 0 1 S0 (~57~1)
- 8 - A 17 LCELL 1 0 0 1 S1 (~57~2)
- 8 - B 20 LCELL 1 0 0 1 S2 (~57~3)
- 7 - B 24 LCELL 1 0 0 1 S3 (~57~4)
- 5 - B 03 LCELL 1 0 0 1 S4 (~57~5)
- 3 - B 22 LCELL 1 0 0 1 S5 (~57~6)
- 6 - B 20 LCELL 1 0 0 1 S6 (~57~7)
- 4 - B 24 LCELL 1 0 0 1 S7 (~57~8)
- 5 - B 23 LCELL 1 0 0 1 S16 (:58)
- 2 - B 05 AND2 ! 0 3 1 4 |74138:37|Y0N (|74138:37|:15)
- 3 - B 03 AND2 ! 0 3 1 4 |74138:37|Y1N (|74138:37|:16)
- 1 - B 03 AND2 ! 0 3 1 4 |74138:37|Y2N (|74138:37|:17)
- 2 - B 03 AND2 ! 0 3 1 4 |74138:37|Y3N (|74138:37|:18)
- 2 - B 02 AND2 ! 0 3 1 4 |74138:37|Y4N (|74138:37|:19)
- 3 - B 02 AND2 ! 0 3 1 5 |74138:37|Y5N (|74138:37|:20)
- 7 - B 02 AND2 ! 0 3 1 4 |74138:37|Y6N (|74138:37|:21)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\edaplay\digital\test7\add8.rpt
add8
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 10/ 96( 10%) 1/ 48( 2%) 11/ 48( 22%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
B: 27/ 96( 28%) 3/ 48( 6%) 19/ 48( 39%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
C: 5/ 96( 5%) 0/ 48( 0%) 0/ 48( 0%) 5/16( 31%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 5/24( 20%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\edaplay\digital\test7\add8.rpt
add8
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 CLK
Device-Specific Information: d:\edaplay\digital\test7\add8.rpt
add8
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
A4 : INPUT;
A5 : INPUT;
A6 : INPUT;
A7 : INPUT;
B0 : INPUT;
B1 : INPUT;
B2 : INPUT;
B3 : INPUT;
B4 : INPUT;
B5 : INPUT;
B6 : INPUT;
B7 : INPUT;
CIN : INPUT;
CLK : INPUT;
-- Node name is 'A'
-- Equation name is 'A', type is output
A = _LC3_A23;
-- Node name is 'B'
-- Equation name is 'B', type is output
B = _LC5_A17;
-- Node name is 'C'
-- Equation name is 'C', type is output
C = _LC7_A13;
-- Node name is 'D'
-- Equation name is 'D', type is output
D = _LC1_A23;
-- Node name is 'E'
-- Equation name is 'E', type is output
E = _LC2_A17;
-- Node name is 'F'
-- Equation name is 'F', type is output
F = _LC4_A17;
-- Node name is 'G'
-- Equation name is 'G', type is output
G = _LC6_A17;
-- Node name is 'H'
-- Equation name is 'H', type is output
H = GND;
-- Node name is '~57~1' = 'S0'
-- Equation name is '~57~1', location is LC8_B24, type is buried.
S0 = LCELL( B0);
-- Node name is '~57~2' = 'S1'
-- Equation name is '~57~2', location is LC8_A17, type is buried.
S1 = LCELL( B1);
-- Node name is '~57~3' = 'S2'
-- Equation name is '~57~3', location is LC8_B20, type is buried.
S2 = LCELL( B2);
-- Node name is '~57~4' = 'S3'
-- Equation name is '~57~4', location is LC7_B24, type is buried.
S3 = LCELL( B3);
-- Node name is '~57~5' = 'S4'
-- Equation name is '~57~5', location is LC5_B3, type is buried.
S4 = LCELL( B4);
-- Node name is '~57~6' = 'S5'
-- Equation name is '~57~6', location is LC3_B22, type is buried.
S5 = LCELL( B5);
-- Node name is '~57~7' = 'S6'
-- Equation name is '~57~7', location is LC6_B20, type is buried.
S6 = LCELL( B6);
-- Node name is '~57~8' = 'S7'
-- Equation name is '~57~8', location is LC4_B24, type is buried.
S7 = LCELL( B7);
-- Node name is '~56~1' = 'S8'
-- Equation name is '~56~1', location is LC6_B3, type is buried.
S8 = LCELL( A0);
-- Node name is '~56~2' = 'S9'
-- Equation name is '~56~2', location is LC4_B22, type is buried.
S9 = LCELL( A1);
-- Node name is '~56~3' = 'S10'
-- Equation name is '~56~3', location is LC4_B20, type is buried.
S10 = LCELL( A2);
-- Node name is '~56~4' = 'S11'
-- Equation name is '~56~4', location is LC2_B24, type is buried.
S11 = LCELL( A3);
-- Node name is '~56~5' = 'S12'
-- Equation name is '~56~5', location is LC2_B13, type is buried.
S12 = LCELL( A4);
-- Node name is '~56~6' = 'S13'
-- Equation name is '~56~6', location is LC5_B22, type is buried.
S13 = LCELL( A5);
-- Node name is '~56~7' = 'S14'
-- Equation name is '~56~7', location is LC2_B20, type is buried.
S14 = LCELL( A6);
-- Node name is '~56~8' = 'S15'
-- Equation name is '~56~8', location is LC2_B19, type is buried.
S15 = LCELL( A7);
-- Node name is ':58' = 'S16'
-- Equation name is 'S16', location is LC5_B23, type is buried.
S16 = LCELL(!CIN);
-- Node name is 'Y0'
-- Equation name is 'Y0', type is output
Y0 = !_LC2_B5;
-- Node name is 'Y1'
-- Equation name is 'Y1', type is output
Y1 = !_LC3_B3;
-- Node name is 'Y2'
-- Equation name is 'Y2', type is output
Y2 = !_LC1_B3;
-- Node name is 'Y3'
-- Equation name is 'Y3', type is output
Y3 = !_LC2_B3;
-- Node name is 'Y4'
-- Equation name is 'Y4', type is output
Y4 = !_LC2_B2;
-- Node name is 'Y5'
-- Equation name is 'Y5', type is output
Y5 = !_LC3_B2;
-- Node name is 'Y6'
-- Equation name is 'Y6', type is output
Y6 = !_LC7_B2;
-- Node name is 'Y7'
-- Equation name is 'Y7', type is output
Y7 = _LC1_B2;
-- Node name is '|ADD4:1|LPM_ADD_SUB:46|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC5_B15', type is buried
_LC5_B15 = LCELL( _EQ001);
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