📄 t5_2.rpt
字号:
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\windows\desktop\edaplay\test5\test5_2\t5_2.rpt
t5_2
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 6/ 48( 12%) 0/ 48( 0%) 1/16( 6%) 4/16( 25%) 0/16( 0%)
B: 2/ 96( 2%) 5/ 48( 10%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\windows\desktop\edaplay\test5\test5_2\t5_2.rpt
t5_2
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 CLK
DFF 3 :49
DFF 3 :48
DFF 3 :44
DFF 3 :43
DFF 3 :42
DFF 3 :36
DFF 3 :35
DFF 3 :34
DFF 3 :30
DFF 3 :29
DFF 3 :28
DFF 3 :50
Device-Specific Information: c:\windows\desktop\edaplay\test5\test5_2\t5_2.rpt
t5_2
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 16 RESET
Device-Specific Information: c:\windows\desktop\edaplay\test5\test5_2\t5_2.rpt
t5_2
** EQUATIONS **
CLK : INPUT;
RESET : INPUT;
-- Node name is 'D0'
-- Equation name is 'D0', type is output
D0 = _LC8_B5;
-- Node name is 'D1'
-- Equation name is 'D1', type is output
D1 = _LC4_B3;
-- Node name is 'D2'
-- Equation name is 'D2', type is output
D2 = _LC1_B3;
-- Node name is 'D3'
-- Equation name is 'D3', type is output
D3 = _LC2_A4;
-- Node name is 'D4'
-- Equation name is 'D4', type is output
D4 = _LC2_B1;
-- Node name is 'D5'
-- Equation name is 'D5', type is output
D5 = _LC1_B1;
-- Node name is 'D6'
-- Equation name is 'D6', type is output
D6 = _LC4_A2;
-- Node name is 'D7'
-- Equation name is 'D7', type is output
D7 = _LC1_A2;
-- Node name is 'D8'
-- Equation name is 'D8', type is output
D8 = _LC3_B5;
-- Node name is 'D9'
-- Equation name is 'D9', type is output
D9 = _LC8_A4;
-- Node name is 'D10'
-- Equation name is 'D10', type is output
D10 = _LC7_A12;
-- Node name is 'D11'
-- Equation name is 'D11', type is output
D11 = _LC1_A12;
-- Node name is 'D12'
-- Equation name is 'D12', type is output
D12 = _LC2_B5;
-- Node name is 'D13'
-- Equation name is 'D13', type is output
D13 = _LC4_B5;
-- Node name is 'D14'
-- Equation name is 'D14', type is output
D14 = _LC6_B7;
-- Node name is 'D15'
-- Equation name is 'D15', type is output
D15 = _LC8_B7;
-- Node name is ':28'
-- Equation name is '_LC8_B5', type is buried
_LC8_B5 = DFFE(!_LC8_B5, GLOBAL( CLK), RESET, VCC, VCC);
-- Node name is ':29'
-- Equation name is '_LC4_B3', type is buried
_LC4_B3 = DFFE(!_LC4_B3, _LC8_B5, RESET, VCC, VCC);
-- Node name is ':30'
-- Equation name is '_LC1_B3', type is buried
_LC1_B3 = DFFE(!_LC1_B3, _LC4_B3, RESET, VCC, VCC);
-- Node name is ':31'
-- Equation name is '_LC2_A4', type is buried
_LC2_A4 = DFFE(!_LC2_A4, _LC1_B3, RESET, VCC, VCC);
-- Node name is ':34'
-- Equation name is '_LC2_B1', type is buried
_LC2_B1 = DFFE(!_LC2_B1, GLOBAL( CLK), RESET, VCC, VCC);
-- Node name is ':35'
-- Equation name is '_LC1_B1', type is buried
_LC1_B1 = DFFE(!_LC1_B1, _LC2_B1, RESET, VCC, VCC);
-- Node name is ':36'
-- Equation name is '_LC4_A2', type is buried
_LC4_A2 = DFFE(!_LC4_A2, _LC1_B1, RESET, VCC, VCC);
-- Node name is ':37'
-- Equation name is '_LC1_A2', type is buried
_LC1_A2 = DFFE(!_LC1_A2, _LC4_A2, RESET, VCC, VCC);
-- Node name is ':42'
-- Equation name is '_LC2_B5', type is buried
_LC2_B5 = DFFE(!_LC2_B5, GLOBAL( CLK), RESET, VCC, VCC);
-- Node name is ':43'
-- Equation name is '_LC4_B5', type is buried
_LC4_B5 = DFFE(!_LC4_B5, _LC2_B5, RESET, VCC, VCC);
-- Node name is ':44'
-- Equation name is '_LC6_B7', type is buried
_LC6_B7 = DFFE(!_LC6_B7, _LC4_B5, RESET, VCC, VCC);
-- Node name is ':45'
-- Equation name is '_LC8_B7', type is buried
_LC8_B7 = DFFE(!_LC8_B7, _LC6_B7, RESET, VCC, VCC);
-- Node name is ':48'
-- Equation name is '_LC3_B5', type is buried
_LC3_B5 = DFFE(!_LC3_B5, GLOBAL( CLK), RESET, VCC, VCC);
-- Node name is ':49'
-- Equation name is '_LC8_A4', type is buried
_LC8_A4 = DFFE(!_LC8_A4, _LC3_B5, RESET, VCC, VCC);
-- Node name is ':50'
-- Equation name is '_LC7_A12', type is buried
_LC7_A12 = DFFE(!_LC7_A12, _LC8_A4, RESET, VCC, VCC);
-- Node name is ':51'
-- Equation name is '_LC1_A12', type is buried
_LC1_A12 = DFFE(!_LC1_A12, _LC7_A12, RESET, VCC, VCC);
Project Information c:\windows\desktop\edaplay\test5\test5_2\t5_2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 9,703K
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