📄 t5_5.rpt
字号:
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 2/ 96( 2%) 5/ 48( 10%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\windows\desktop\edaplay\test5\test5_5\t5_5.rpt
t5_5
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 CLK
Device-Specific Information: c:\windows\desktop\edaplay\test5\test5_5\t5_5.rpt
t5_5
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 4 |hb1:15|:35
LCELL 4 |hb3:18|:35
Device-Specific Information: c:\windows\desktop\edaplay\test5\test5_5\t5_5.rpt
t5_5
** EQUATIONS **
CLK : INPUT;
-- Node name is 'A0'
-- Equation name is 'A0', type is output
A0 = _LC2_B6;
-- Node name is 'A1'
-- Equation name is 'A1', type is output
A1 = _LC7_B3;
-- Node name is 'A2'
-- Equation name is 'A2', type is output
A2 = _LC1_B3;
-- Node name is 'A3'
-- Equation name is 'A3', type is output
A3 = _LC3_B3;
-- Node name is 'B0'
-- Equation name is 'B0', type is output
B0 = _LC2_A2;
-- Node name is 'B1'
-- Equation name is 'B1', type is output
B1 = _LC6_A2;
-- Node name is 'B2'
-- Equation name is 'B2', type is output
B2 = _LC4_A2;
-- Node name is 'B3'
-- Equation name is 'B3', type is output
B3 = _LC1_A2;
-- Node name is 'C0'
-- Equation name is 'C0', type is output
C0 = _LC3_A9;
-- Node name is 'C1'
-- Equation name is 'C1', type is output
C1 = _LC5_A9;
-- Node name is 'C2'
-- Equation name is 'C2', type is output
C2 = _LC7_A9;
-- Node name is 'C3'
-- Equation name is 'C3', type is output
C3 = _LC1_A9;
-- Node name is 'D0'
-- Equation name is 'D0', type is output
D0 = _LC2_B4;
-- Node name is 'D1'
-- Equation name is 'D1', type is output
D1 = _LC3_B4;
-- Node name is 'D2'
-- Equation name is 'D2', type is output
D2 = _LC6_B4;
-- Node name is 'D3'
-- Equation name is 'D3', type is output
D3 = _LC8_B4;
-- Node name is '|hb1:15|:35' from file "hb1.tdf" line 8, column 9
-- Equation name is '_LC2_B3', type is buried
!_LC2_B3 = _LC2_B3~NOT;
_LC2_B3~NOT = LCELL( _EQ001);
_EQ001 = !_LC1_B3 & !_LC3_B3
# !_LC3_B3 & !_LC7_B3;
-- Node name is '|hb3:18|:35' from file "hb3.tdf" line 8, column 9
-- Equation name is '_LC2_A9', type is buried
!_LC2_A9 = _LC2_A9~NOT;
_LC2_A9~NOT = LCELL( _EQ002);
_EQ002 = !_LC7_A9
# !_LC1_A9;
-- Node name is '|74161:2|f74161:sub|:9' = '|74161:2|f74161:sub|QA'
-- Equation name is '_LC2_B6', type is buried
_LC2_B6 = DFFE(!_LC2_B6, GLOBAL( CLK), !_LC2_B3, VCC, VCC);
-- Node name is '|74161:2|f74161:sub|:87' = '|74161:2|f74161:sub|QB'
-- Equation name is '_LC7_B3', type is buried
_LC7_B3 = DFFE( _EQ003, GLOBAL( CLK), !_LC2_B3, VCC, VCC);
_EQ003 = _LC2_B6 & !_LC7_B3
# !_LC2_B6 & _LC7_B3;
-- Node name is '|74161:2|f74161:sub|:99' = '|74161:2|f74161:sub|QC'
-- Equation name is '_LC1_B3', type is buried
_LC1_B3 = DFFE( _EQ004, GLOBAL( CLK), !_LC2_B3, VCC, VCC);
_EQ004 = _LC1_B3 & !_LC2_B6
# _LC1_B3 & !_LC7_B3
# !_LC1_B3 & _LC2_B6 & _LC7_B3;
-- Node name is '|74161:2|f74161:sub|:110' = '|74161:2|f74161:sub|QD'
-- Equation name is '_LC3_B3', type is buried
_LC3_B3 = DFFE( _EQ005, GLOBAL( CLK), !_LC2_B3, VCC, VCC);
_EQ005 = !_LC2_B6 & _LC3_B3
# _LC3_B3 & !_LC7_B3
# !_LC1_B3 & _LC3_B3
# _LC1_B3 & _LC2_B6 & !_LC3_B3 & _LC7_B3;
-- Node name is '|74161:3|f74161:sub|:9' = '|74161:3|f74161:sub|QA'
-- Equation name is '_LC2_A2', type is buried
_LC2_A2 = DFFE( _EQ006, GLOBAL( CLK), VCC, VCC, VCC);
_EQ006 = !_LC2_A2
# _LC1_A2
# !_LC4_A2 & !_LC6_A2;
-- Node name is '|74161:3|f74161:sub|:87' = '|74161:3|f74161:sub|QB'
-- Equation name is '_LC6_A2', type is buried
_LC6_A2 = DFFE( _EQ007, GLOBAL( CLK), VCC, VCC, VCC);
_EQ007 = _LC1_A2
# !_LC4_A2 & !_LC6_A2
# !_LC2_A2 & !_LC4_A2
# !_LC2_A2 & _LC6_A2
# _LC2_A2 & !_LC6_A2;
-- Node name is '|74161:3|f74161:sub|:99' = '|74161:3|f74161:sub|QC'
-- Equation name is '_LC4_A2', type is buried
_LC4_A2 = DFFE( _EQ008, GLOBAL( CLK), VCC, VCC, VCC);
_EQ008 = !_LC1_A2 & _LC4_A2 & !_LC6_A2
# !_LC1_A2 & !_LC2_A2 & _LC4_A2
# !_LC1_A2 & _LC2_A2 & !_LC4_A2 & _LC6_A2;
-- Node name is '|74161:3|f74161:sub|:110' = '|74161:3|f74161:sub|QD'
-- Equation name is '_LC1_A2', type is buried
_LC1_A2 = DFFE( _EQ009, GLOBAL( CLK), VCC, VCC, VCC);
_EQ009 = !_LC1_A2 & _LC2_A2 & _LC4_A2 & _LC6_A2;
-- Node name is '|74161:4|f74161:sub|:9' = '|74161:4|f74161:sub|QA'
-- Equation name is '_LC3_A9', type is buried
_LC3_A9 = DFFE(!_LC3_A9, GLOBAL( CLK), !_LC2_A9, VCC, VCC);
-- Node name is '|74161:4|f74161:sub|:87' = '|74161:4|f74161:sub|QB'
-- Equation name is '_LC5_A9', type is buried
_LC5_A9 = DFFE( _EQ010, GLOBAL( CLK), !_LC2_A9, VCC, VCC);
_EQ010 = _LC3_A9 & !_LC5_A9
# !_LC3_A9 & _LC5_A9;
-- Node name is '|74161:4|f74161:sub|:99' = '|74161:4|f74161:sub|QC'
-- Equation name is '_LC7_A9', type is buried
_LC7_A9 = DFFE( _EQ011, GLOBAL( CLK), !_LC2_A9, VCC, VCC);
_EQ011 = !_LC3_A9 & _LC7_A9
# !_LC5_A9 & _LC7_A9
# _LC3_A9 & _LC5_A9 & !_LC7_A9;
-- Node name is '|74161:4|f74161:sub|:110' = '|74161:4|f74161:sub|QD'
-- Equation name is '_LC1_A9', type is buried
_LC1_A9 = DFFE( _EQ012, GLOBAL( CLK), !_LC2_A9, VCC, VCC);
_EQ012 = _LC1_A9 & !_LC7_A9
# _LC1_A9 & !_LC3_A9
# _LC1_A9 & !_LC5_A9
# !_LC1_A9 & _LC3_A9 & _LC5_A9 & _LC7_A9;
-- Node name is '|74161:5|f74161:sub|:9' = '|74161:5|f74161:sub|QA'
-- Equation name is '_LC2_B4', type is buried
_LC2_B4 = DFFE( _EQ013, GLOBAL( CLK), VCC, VCC, VCC);
_EQ013 = !_LC2_B4
# !_LC3_B4 & !_LC6_B4 & !_LC8_B4;
-- Node name is '|74161:5|f74161:sub|:87' = '|74161:5|f74161:sub|QB'
-- Equation name is '_LC3_B4', type is buried
_LC3_B4 = DFFE( _EQ014, GLOBAL( CLK), VCC, VCC, VCC);
_EQ014 = !_LC2_B4 & _LC3_B4
# _LC2_B4 & !_LC3_B4
# !_LC3_B4 & !_LC6_B4 & !_LC8_B4
# !_LC2_B4 & !_LC6_B4 & !_LC8_B4;
-- Node name is '|74161:5|f74161:sub|:99' = '|74161:5|f74161:sub|QC'
-- Equation name is '_LC6_B4', type is buried
_LC6_B4 = DFFE( _EQ015, GLOBAL( CLK), VCC, VCC, VCC);
_EQ015 = !_LC3_B4 & _LC6_B4
# _LC2_B4 & _LC3_B4 & !_LC6_B4
# !_LC2_B4 & _LC6_B4 & !_LC8_B4;
-- Node name is '|74161:5|f74161:sub|:110' = '|74161:5|f74161:sub|QD'
-- Equation name is '_LC8_B4', type is buried
_LC8_B4 = DFFE( _EQ016, GLOBAL( CLK), VCC, VCC, VCC);
_EQ016 = !_LC3_B4 & _LC8_B4
# !_LC6_B4 & _LC8_B4
# _LC2_B4 & _LC3_B4 & _LC6_B4 & !_LC8_B4;
Project Information c:\windows\desktop\edaplay\test5\test5_5\t5_5.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 10,602K
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