📄 t5_3.rpt
字号:
- 6 - A 04 DFFE + 1 2 1 2 |74161:4|f74161:sub|QC (|74161:4|f74161:sub|:99)
- 1 - A 04 AND2 0 4 0 4 |74161:4|f74161:sub|:104
- 4 - A 04 DFFE + 1 3 1 1 |74161:4|f74161:sub|QD (|74161:4|f74161:sub|:110)
- 2 - A 02 DFFE + 1 1 1 3 |74161:5|f74161:sub|QA (|74161:5|f74161:sub|:9)
- 4 - A 02 DFFE + 1 2 1 2 |74161:5|f74161:sub|QB (|74161:5|f74161:sub|:87)
- 3 - A 02 AND2 0 3 0 1 |74161:5|f74161:sub|:96
- 6 - A 02 DFFE + 1 3 1 1 |74161:5|f74161:sub|QC (|74161:5|f74161:sub|:99)
- 1 - A 02 DFFE + 1 2 1 0 |74161:5|f74161:sub|QD (|74161:5|f74161:sub|:110)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\edaplay\digital\test5\test5_3\t5_3.rpt
t5_3
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 3/ 48( 6%) 0/ 48( 0%) 1/16( 6%) 1/16( 6%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\edaplay\digital\test5\test5_3\t5_3.rpt
t5_3
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 CLK
Device-Specific Information: d:\edaplay\digital\test5\test5_3\t5_3.rpt
t5_3
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 RESET
Device-Specific Information: d:\edaplay\digital\test5\test5_3\t5_3.rpt
t5_3
** EQUATIONS **
CLK : INPUT;
RESET : INPUT;
-- Node name is 'D0'
-- Equation name is 'D0', type is output
D0 = _LC4_A6;
-- Node name is 'D1'
-- Equation name is 'D1', type is output
D1 = _LC2_A4;
-- Node name is 'D2'
-- Equation name is 'D2', type is output
D2 = _LC6_A4;
-- Node name is 'D3'
-- Equation name is 'D3', type is output
D3 = _LC4_A4;
-- Node name is 'D4'
-- Equation name is 'D4', type is output
D4 = _LC2_A2;
-- Node name is 'D5'
-- Equation name is 'D5', type is output
D5 = _LC4_A2;
-- Node name is 'D6'
-- Equation name is 'D6', type is output
D6 = _LC6_A2;
-- Node name is 'D7'
-- Equation name is 'D7', type is output
D7 = _LC1_A2;
-- Node name is '|74161:4|f74161:sub|:9' = '|74161:4|f74161:sub|QA'
-- Equation name is '_LC4_A6', type is buried
_LC4_A6 = DFFE(!_LC4_A6, GLOBAL( CLK), RESET, VCC, VCC);
-- Node name is '|74161:4|f74161:sub|:87' = '|74161:4|f74161:sub|QB'
-- Equation name is '_LC2_A4', type is buried
_LC2_A4 = DFFE( _EQ001, GLOBAL( CLK), RESET, VCC, VCC);
_EQ001 = _LC2_A4 & !_LC4_A6
# !_LC2_A4 & _LC4_A6;
-- Node name is '|74161:4|f74161:sub|:99' = '|74161:4|f74161:sub|QC'
-- Equation name is '_LC6_A4', type is buried
_LC6_A4 = DFFE( _EQ002, GLOBAL( CLK), RESET, VCC, VCC);
_EQ002 = !_LC2_A4 & _LC6_A4
# !_LC4_A6 & _LC6_A4
# _LC2_A4 & _LC4_A6 & !_LC6_A4;
-- Node name is '|74161:4|f74161:sub|:110' = '|74161:4|f74161:sub|QD'
-- Equation name is '_LC4_A4', type is buried
_LC4_A4 = DFFE( _EQ003, GLOBAL( CLK), RESET, VCC, VCC);
_EQ003 = !_LC2_A4 & _LC4_A4
# _LC4_A4 & !_LC4_A6
# _LC4_A4 & !_LC6_A4
# _LC2_A4 & !_LC4_A4 & _LC4_A6 & _LC6_A4;
-- Node name is '|74161:4|f74161:sub|:104'
-- Equation name is '_LC1_A4', type is buried
_LC1_A4 = LCELL( _EQ004);
_EQ004 = _LC2_A4 & _LC4_A4 & _LC4_A6 & _LC6_A4;
-- Node name is '|74161:5|f74161:sub|:9' = '|74161:5|f74161:sub|QA'
-- Equation name is '_LC2_A2', type is buried
_LC2_A2 = DFFE( _EQ005, GLOBAL( CLK), RESET, VCC, VCC);
_EQ005 = !_LC1_A4 & _LC2_A2
# _LC1_A4 & !_LC2_A2;
-- Node name is '|74161:5|f74161:sub|:87' = '|74161:5|f74161:sub|QB'
-- Equation name is '_LC4_A2', type is buried
_LC4_A2 = DFFE( _EQ006, GLOBAL( CLK), RESET, VCC, VCC);
_EQ006 = !_LC2_A2 & _LC4_A2
# !_LC1_A4 & _LC4_A2
# _LC1_A4 & _LC2_A2 & !_LC4_A2;
-- Node name is '|74161:5|f74161:sub|:99' = '|74161:5|f74161:sub|QC'
-- Equation name is '_LC6_A2', type is buried
_LC6_A2 = DFFE( _EQ007, GLOBAL( CLK), RESET, VCC, VCC);
_EQ007 = !_LC4_A2 & _LC6_A2
# !_LC2_A2 & _LC6_A2
# !_LC1_A4 & _LC6_A2
# _LC1_A4 & _LC2_A2 & _LC4_A2 & !_LC6_A2;
-- Node name is '|74161:5|f74161:sub|:110' = '|74161:5|f74161:sub|QD'
-- Equation name is '_LC1_A2', type is buried
_LC1_A2 = DFFE( _EQ008, GLOBAL( CLK), RESET, VCC, VCC);
_EQ008 = _LC1_A2 & !_LC6_A2
# _LC1_A2 & !_LC3_A2
# !_LC1_A2 & _LC3_A2 & _LC6_A2;
-- Node name is '|74161:5|f74161:sub|:96'
-- Equation name is '_LC3_A2', type is buried
_LC3_A2 = LCELL( _EQ009);
_EQ009 = _LC1_A4 & _LC2_A2 & _LC4_A2;
Project Information d:\edaplay\digital\test5\test5_3\t5_3.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,978K
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