add4.vhd

来自「几个VHDL实现的源程序及其代码」· VHDL 代码 · 共 24 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY ADD4 IS
PORT(
CIN :  IN STD_LOGIC;
A   :  IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B   :  IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S   : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT: OUT STD_LOGIC);
END ADD4;

ARCHITECTURE BEHAV OF ADD4 IS
SIGNAL SINT:STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL AA,BB:STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
AA<='0' & A;
BB<='0' & B;
SINT<=AA+BB+CIN;
S<=SINT(3 DOWNTO 0);
COUT<=SINT(4);
END BEHAV;