📄 mul8x8.rpt
字号:
|add16:8|add8:2|add4:2|lpm_add_sub:47|
|add16:8|add8:2|add4:2|lpm_add_sub:47|addcore:adder|
|add16:8|add8:2|add4:2|lpm_add_sub:47|altshift:result_ext_latency_ffs|
|add16:8|add8:2|add4:2|lpm_add_sub:47|altshift:carry_ext_latency_ffs|
|add16:8|add8:2|add4:2|lpm_add_sub:47|altshift:oflow_ext_latency_ffs|
|add16:4|
|add16:4|add8:1|
|add16:4|add8:1|add4:1|
|add16:4|add8:1|add4:1|lpm_add_sub:46|
|add16:4|add8:1|add4:1|lpm_add_sub:46|addcore:adder|
|add16:4|add8:1|add4:1|lpm_add_sub:46|altshift:result_ext_latency_ffs|
|add16:4|add8:1|add4:1|lpm_add_sub:46|altshift:carry_ext_latency_ffs|
|add16:4|add8:1|add4:1|lpm_add_sub:46|altshift:oflow_ext_latency_ffs|
|add16:4|add8:1|add4:1|lpm_add_sub:47|
|add16:4|add8:1|add4:1|lpm_add_sub:47|addcore:adder|
|add16:4|add8:1|add4:1|lpm_add_sub:47|altshift:result_ext_latency_ffs|
|add16:4|add8:1|add4:1|lpm_add_sub:47|altshift:carry_ext_latency_ffs|
|add16:4|add8:1|add4:1|lpm_add_sub:47|altshift:oflow_ext_latency_ffs|
|add16:4|add8:1|add4:2|
|add16:4|add8:1|add4:2|lpm_add_sub:46|
|add16:4|add8:1|add4:2|lpm_add_sub:46|addcore:adder|
|add16:4|add8:1|add4:2|lpm_add_sub:46|altshift:result_ext_latency_ffs|
|add16:4|add8:1|add4:2|lpm_add_sub:46|altshift:carry_ext_latency_ffs|
|add16:4|add8:1|add4:2|lpm_add_sub:46|altshift:oflow_ext_latency_ffs|
|add16:4|add8:1|add4:2|lpm_add_sub:47|
|add16:4|add8:1|add4:2|lpm_add_sub:47|addcore:adder|
|add16:4|add8:1|add4:2|lpm_add_sub:47|altshift:result_ext_latency_ffs|
|add16:4|add8:1|add4:2|lpm_add_sub:47|altshift:carry_ext_latency_ffs|
|add16:4|add8:1|add4:2|lpm_add_sub:47|altshift:oflow_ext_latency_ffs|
|add16:4|add8:2|
|add16:4|add8:2|add4:1|
|add16:4|add8:2|add4:1|lpm_add_sub:46|
|add16:4|add8:2|add4:1|lpm_add_sub:46|addcore:adder|
|add16:4|add8:2|add4:1|lpm_add_sub:46|altshift:result_ext_latency_ffs|
|add16:4|add8:2|add4:1|lpm_add_sub:46|altshift:carry_ext_latency_ffs|
|add16:4|add8:2|add4:1|lpm_add_sub:46|altshift:oflow_ext_latency_ffs|
|add16:4|add8:2|add4:1|lpm_add_sub:47|
|add16:4|add8:2|add4:1|lpm_add_sub:47|addcore:adder|
|add16:4|add8:2|add4:1|lpm_add_sub:47|altshift:result_ext_latency_ffs|
|add16:4|add8:2|add4:1|lpm_add_sub:47|altshift:carry_ext_latency_ffs|
|add16:4|add8:2|add4:1|lpm_add_sub:47|altshift:oflow_ext_latency_ffs|
|add16:4|add8:2|add4:2|
|add16:4|add8:2|add4:2|lpm_add_sub:46|
|add16:4|add8:2|add4:2|lpm_add_sub:46|addcore:adder|
|add16:4|add8:2|add4:2|lpm_add_sub:46|altshift:result_ext_latency_ffs|
|add16:4|add8:2|add4:2|lpm_add_sub:46|altshift:carry_ext_latency_ffs|
|add16:4|add8:2|add4:2|lpm_add_sub:46|altshift:oflow_ext_latency_ffs|
|add16:4|add8:2|add4:2|lpm_add_sub:47|
|add16:4|add8:2|add4:2|lpm_add_sub:47|addcore:adder|
|add16:4|add8:2|add4:2|lpm_add_sub:47|altshift:result_ext_latency_ffs|
|add16:4|add8:2|add4:2|lpm_add_sub:47|altshift:carry_ext_latency_ffs|
|add16:4|add8:2|add4:2|lpm_add_sub:47|altshift:oflow_ext_latency_ffs|
|mul8x1:27|
|mul8x1:22|
|mul8x1:23|
|mul8x1:24|
|mul8x1:26|
|mul8x1:25|
|mul8x1:21|
|mul8x1:20|
|seltime:34|
|seltime:34|lpm_add_sub:76|
|seltime:34|lpm_add_sub:76|addcore:adder|
|seltime:34|lpm_add_sub:76|altshift:result_ext_latency_ffs|
|seltime:34|lpm_add_sub:76|altshift:carry_ext_latency_ffs|
|seltime:34|lpm_add_sub:76|altshift:oflow_ext_latency_ffs|
|deled:33|
|74138:44|
Device-Specific Information: c:\windows\desktop\aaaaaaa\mul8x8.rpt
mul8x8
***** Logic for device 'mul8x8' compiled without errors.
Device: EPF10K10LC84-4
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
^
C
R R R R O
E E E E N
V S G c G S G S S F
C E N l N E N E E _ ^
C R D k D R D R R # D n
I V I d I V I V V T O C
y y y y y y y N E N s N E N E E b b C N E
6 5 4 3 2 1 0 T D T p T D T D D 0 1 K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | b2
^nCE | 14 72 | b3
#TDI | 15 71 | b4
y7 | 16 70 | b5
a | 17 69 | RESERVED
b | 18 68 | GNDINT
c | 19 67 | b6
VCCINT | 20 66 | b7
d | 21 65 | a0
e | 22 EPF10K10LC84-4 64 | a1
f | 23 63 | VCCINT
g | 24 62 | a2
h | 25 61 | a3
GNDINT | 26 60 | a4
RESERVED | 27 59 | a5
RESERVED | 28 58 | a6
RESERVED | 29 57 | #TMS
RESERVED | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | a7
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ R R R R R V G G G G V G R R R R R R R
C n E E E E E C N N N N C N E E E E E E E
C C S S S S S C D D D D C D S S S S S S S
I O E E E E E I I I I I I I E E E E E E E
N N R R R R R N N N N N N N R R R R R R R
T F V V V V V T T T T T T T V V V V V V V
I E E E E E E E E E E E E
G D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: c:\windows\desktop\aaaaaaa\mul8x8.rpt
mul8x8
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A2 8/ 8(100%) 3/ 8( 37%) 6/ 8( 75%) 1/2 0/2 5/22( 22%)
A4 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
A5 5/ 8( 62%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
A6 7/ 8( 87%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
A9 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 4/22( 18%)
A10 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 6/22( 27%)
A14 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 7/22( 31%)
A15 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 5/22( 22%)
A16 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 9/22( 40%)
A17 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 6/22( 27%)
A18 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 6/22( 27%)
A19 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 11/22( 50%)
A20 6/ 8( 75%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 2/22( 9%)
A22 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 9/22( 40%)
A23 6/ 8( 75%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
A24 4/ 8( 50%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 6/22( 27%)
B1 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 6/22( 27%)
B2 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
B3 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
B4 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
B5 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
B6 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
B7 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
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