andarith.vhd

来自「几个VHDL实现的源程序及其代码」· VHDL 代码 · 共 21 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY ANDARITH IS
PORT(
ABIN:IN STD_LOGIC;
DIN :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ANDARITH;

ARCHITECTURE BEHAV OF ANDARITH IS
BEGIN
PROCESS(ABIN,DIN)
BEGIN
FOR I IN 0 TO 7 LOOP
DOUT(I)<=DIN(I) AND ABIN;
END LOOP;
END PROCESS;
END BEHAV;