mul8x1.tdo

几个VHDL实现的源程序及其代码

--	MAX+plus II Version 10.2 06/28/2002
--	Created: 10/20/2002 16:46:38

-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.


SUBDESIGN 'mul8x1'
(
    a                  : INPUT;
    a0                 : INPUT;
    a1                 : INPUT;
    a2                 : INPUT;
    b0                 : INPUT;
    b1                 : INPUT;
    b2                 : INPUT;
    b3                 : INPUT;
    b4                 : INPUT;
    b5                 : INPUT;
    b6                 : INPUT;
    b7                 : INPUT;
    c0                 : OUTPUT;
    c1                 : OUTPUT;
    c2                 : OUTPUT;
    c3                 : OUTPUT;
    c4                 : OUTPUT;
    c5                 : OUTPUT;
    c6                 : OUTPUT;
    c7                 : OUTPUT;
    c8                 : OUTPUT;
    c9                 : OUTPUT;
    c10                : OUTPUT;
    c11                : OUTPUT;
    c12                : OUTPUT;
    c13                : OUTPUT;
    c14                : OUTPUT;
    c15                : OUTPUT;
)

VARIABLE

    _EQ001             : NODE;
    _EQ002             : NODE;
    _EQ003             : NODE;
    _EQ004             : NODE;
    _EQ005             : NODE;
    _EQ006             : NODE;
    _EQ007             : NODE;
    _EQ008             : NODE;
    _EQ009             : NODE;
    _EQ010             : NODE;
    _EQ011             : NODE;
    _EQ012             : NODE;
    _EQ013             : NODE;
    _EQ014             : NODE;
    _EQ015             : NODE;
    _EQ016             : NODE;
    _EQ017             : NODE;
    _LC5_C14           : NODE;
    _LC2_A16           : NODE;
    _LC2_C14           : NODE;
    _LC8_C14           : NODE;
    _LC6_C14           : NODE;
    _LC7_C14           : NODE;
    _LC3_C14           : NODE;
    _LC4_C14           : NODE;
    _LC1_C14           : NODE;
    _LC4_B8            : NODE;
    _LC6_B8            : NODE;
    _LC5_B8            : NODE;
    _LC7_B8            : NODE;
    _LC2_B8            : NODE;
    _LC1_B8            : NODE;
    _LC3_B8            : NODE;
    _LC8_B8            : NODE;

BEGIN

-- Node name is 'c0' 
c0       =  _LC8_B8;

-- Node name is 'c1' 
c1       =  _LC3_B8;

-- Node name is 'c2' 
c2       =  _LC1_B8;

-- Node name is 'c3' 
c3       =  _LC2_B8;

-- Node name is 'c4' 
c4       =  _LC7_B8;

-- Node name is 'c5' 
c5       =  _LC5_B8;

-- Node name is 'c6' 
c6       =  _LC6_B8;

-- Node name is 'c7' 
c7       =  _LC4_B8;

-- Node name is 'c8' 
c8       =  _LC1_C14;

-- Node name is 'c9' 
c9       =  _LC4_C14;

-- Node name is 'c10' 
c10      =  _LC3_C14;

-- Node name is 'c11' 
c11      =  _LC7_C14;

-- Node name is 'c12' 
c12      =  _LC6_C14;

-- Node name is 'c13' 
c13      =  _LC8_C14;

-- Node name is 'c14' 
c14      =  _LC2_C14;

-- Node name is 'c15' 
c15      =  _LC2_A16;

-- Node name is ':1187' 
_LC5_C14 = LCELL( _EQ001);
  _EQ001 = !a0 & !a1 & !a2;

-- Node name is ':1442' 
_LC2_A16 = LCELL( _EQ002);
  _EQ002 =  a &  _LC2_A16;

-- Node name is ':1448' 
_LC2_C14 = LCELL( _EQ003);
  _EQ003 =  a &  _LC2_C14;

-- Node name is ':1454' 
_LC8_C14 = LCELL( _EQ004);
  _EQ004 =  a &  _LC8_C14;

-- Node name is ':1460' 
_LC6_C14 = LCELL( _EQ005);
  _EQ005 =  a &  _LC6_C14;

-- Node name is ':1466' 
_LC7_C14 = LCELL( _EQ006);
  _EQ006 =  a &  _LC7_C14;

-- Node name is ':1472' 
_LC3_C14 = LCELL( _EQ007);
  _EQ007 =  a &  _LC3_C14;

-- Node name is ':1478' 
_LC4_C14 = LCELL( _EQ008);
  _EQ008 =  a &  _LC4_C14;

-- Node name is ':1484' 
_LC1_C14 = LCELL( _EQ009);
  _EQ009 =  a &  _LC1_C14 &  _LC5_C14
         #  a &  b7 & !_LC5_C14;

-- Node name is ':1491' 
_LC4_B8  = LCELL( _EQ010);
  _EQ010 =  a &  b6 & !_LC5_C14
         #  a &  b7 &  _LC5_C14;

-- Node name is ':1497' 
_LC6_B8  = LCELL( _EQ011);
  _EQ011 =  a &  b5 & !_LC5_C14
         #  a &  b6 &  _LC5_C14;

-- Node name is ':1503' 
_LC5_B8  = LCELL( _EQ012);
  _EQ012 =  a &  b4 & !_LC5_C14
         #  a &  b5 &  _LC5_C14;

-- Node name is ':1509' 
_LC7_B8  = LCELL( _EQ013);
  _EQ013 =  a &  b3 & !_LC5_C14
         #  a &  b4 &  _LC5_C14;

-- Node name is ':1515' 
_LC2_B8  = LCELL( _EQ014);
  _EQ014 =  a &  b2 & !_LC5_C14
         #  a &  b3 &  _LC5_C14;

-- Node name is ':1521' 
_LC1_B8  = LCELL( _EQ015);
  _EQ015 =  a &  b1 & !_LC5_C14
         #  a &  b2 &  _LC5_C14;

-- Node name is ':1527' 
_LC3_B8  = LCELL( _EQ016);
  _EQ016 =  a &  b0 & !_LC5_C14
         #  a &  b1 &  _LC5_C14;

-- Node name is ':1532' 
_LC8_B8  = LCELL( _EQ017);
  _EQ017 =  a & !_LC5_C14 &  _LC8_B8
         #  a &  b0 &  _LC5_C14;


END;