arictl.vhd

来自「几个VHDL实现的源程序及其代码」· VHDL 代码 · 共 46 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY ARICTL IS
PORT(
CLK: IN STD_LOGIC;
start:in std_logic;
CLKOUT: OUT STD_LOGIC;
rstall:out std_logic;
ARIEND: OUT STD_LOGIC);
END ARICTL;

architecture behav of arictl is
signal cnt4b : std_logic_vector(3 downto 0);
begin
rstall<=start;
process(clk,start)
begin
if start='1' then cnt4b<="0000";
elsif clk'event and clk='1' then
   if cnt4b<8 then 
      cnt4b<=cnt4b+1;
   end if;
end if;
end process;

process(clk,cnt4b,start)
begin
  if start='0' then
     if cnt4b<8 then
       clkout<=clk;
       ariend<='0';
    else
       clkout<='0';
       ariend<='1';
    end if;
  else 
    clkout<=clk;
    ariend<='0';
  end if;
end process;
end behav;