mul8x1.vhd

几个VHDL实现的源程序及其代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity mul8x1 is
  port(a:in std_logic;
       a2,a1,a0:in std_logic;
       b:in std_logic_vector(7 downto 0);
       c:out std_logic_vector(15 downto 0));
end;

architecture one of mul8x1 is
signal d: std_logic_vector(15 downto 0):="0000000000000000";
signal cin:std_logic_vector(2 downto 0);
begin
cin<=a2&a1&a0;
process(cin,a)
begin
if a='1' then
  case cin is
    when "000"=>d(7 downto 0)<=b;
    when "001"=>d(8 downto 1)<=b;
    when "010"=>d(9 downto 2)<=b;
    when "011"=>d(10 downto 3)<=b;
    when "100"=>d(11 downto 4)<=b;
    when "101"=>d(12 downto 5)<=b;
    when "110"=>d(13 downto 6)<=b;
    when "111"=>d(14 downto 7)<=b;
    when others=>d<="0000000000000000";
  end case;
else
  d<="0000000000000000";
end if;
c<=d;
end process;
end;