reg16b.vhd

来自「几个VHDL实现的源程序及其代码」· VHDL 代码 · 共 26 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY REG16B IS
PORT(
CLK: IN STD_LOGIC;
CLR: IN STD_LOGIC;
D: IN STD_LOGIC_VECTOR(8 DOWNTO 0);
Q: OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END REG16B;

ARCHITECTURE BEHAV OF REG16B IS
SIGNAL R16S:STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
PROCESS(CLK,CLR)
BEGIN
IF CLR='1' THEN
R16S<=(OTHERS=>'0');
ELSIF CLK'EVENT AND CLK='1' THEN
R16S(6 DOWNTO 0)<=R16S(7 DOWNTO 1);
R16S(15 DOWNTO 7)<=D;
END IF;
END PROCESS;
Q<=R16S;
END BEHAV;