📄 mul8x1.rpt
字号:
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\windows\desktop\aaaaaaa\mul8x1.rpt
mul8x1
** EQUATIONS **
a : INPUT;
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
b4 : INPUT;
b5 : INPUT;
b6 : INPUT;
b7 : INPUT;
-- Node name is 'c0'
-- Equation name is 'c0', type is output
c0 = _LC8_B8;
-- Node name is 'c1'
-- Equation name is 'c1', type is output
c1 = _LC3_B8;
-- Node name is 'c2'
-- Equation name is 'c2', type is output
c2 = _LC1_B8;
-- Node name is 'c3'
-- Equation name is 'c3', type is output
c3 = _LC2_B8;
-- Node name is 'c4'
-- Equation name is 'c4', type is output
c4 = _LC7_B8;
-- Node name is 'c5'
-- Equation name is 'c5', type is output
c5 = _LC5_B8;
-- Node name is 'c6'
-- Equation name is 'c6', type is output
c6 = _LC6_B8;
-- Node name is 'c7'
-- Equation name is 'c7', type is output
c7 = _LC4_B8;
-- Node name is 'c8'
-- Equation name is 'c8', type is output
c8 = _LC1_C14;
-- Node name is 'c9'
-- Equation name is 'c9', type is output
c9 = _LC4_C14;
-- Node name is 'c10'
-- Equation name is 'c10', type is output
c10 = _LC3_C14;
-- Node name is 'c11'
-- Equation name is 'c11', type is output
c11 = _LC7_C14;
-- Node name is 'c12'
-- Equation name is 'c12', type is output
c12 = _LC6_C14;
-- Node name is 'c13'
-- Equation name is 'c13', type is output
c13 = _LC8_C14;
-- Node name is 'c14'
-- Equation name is 'c14', type is output
c14 = _LC2_C14;
-- Node name is 'c15'
-- Equation name is 'c15', type is output
c15 = _LC2_A16;
-- Node name is ':1187'
-- Equation name is '_LC5_C14', type is buried
_LC5_C14 = LCELL( _EQ001);
_EQ001 = !a0 & !a1 & !a2;
-- Node name is ':1442'
-- Equation name is '_LC2_A16', type is buried
_LC2_A16 = LCELL( _EQ002);
_EQ002 = a & _LC2_A16;
-- Node name is ':1448'
-- Equation name is '_LC2_C14', type is buried
_LC2_C14 = LCELL( _EQ003);
_EQ003 = a & _LC2_C14;
-- Node name is ':1454'
-- Equation name is '_LC8_C14', type is buried
_LC8_C14 = LCELL( _EQ004);
_EQ004 = a & _LC8_C14;
-- Node name is ':1460'
-- Equation name is '_LC6_C14', type is buried
_LC6_C14 = LCELL( _EQ005);
_EQ005 = a & _LC6_C14;
-- Node name is ':1466'
-- Equation name is '_LC7_C14', type is buried
_LC7_C14 = LCELL( _EQ006);
_EQ006 = a & _LC7_C14;
-- Node name is ':1472'
-- Equation name is '_LC3_C14', type is buried
_LC3_C14 = LCELL( _EQ007);
_EQ007 = a & _LC3_C14;
-- Node name is ':1478'
-- Equation name is '_LC4_C14', type is buried
_LC4_C14 = LCELL( _EQ008);
_EQ008 = a & _LC4_C14;
-- Node name is ':1484'
-- Equation name is '_LC1_C14', type is buried
_LC1_C14 = LCELL( _EQ009);
_EQ009 = a & _LC1_C14 & _LC5_C14
# a & b7 & !_LC5_C14;
-- Node name is ':1491'
-- Equation name is '_LC4_B8', type is buried
_LC4_B8 = LCELL( _EQ010);
_EQ010 = a & b6 & !_LC5_C14
# a & b7 & _LC5_C14;
-- Node name is ':1497'
-- Equation name is '_LC6_B8', type is buried
_LC6_B8 = LCELL( _EQ011);
_EQ011 = a & b5 & !_LC5_C14
# a & b6 & _LC5_C14;
-- Node name is ':1503'
-- Equation name is '_LC5_B8', type is buried
_LC5_B8 = LCELL( _EQ012);
_EQ012 = a & b4 & !_LC5_C14
# a & b5 & _LC5_C14;
-- Node name is ':1509'
-- Equation name is '_LC7_B8', type is buried
_LC7_B8 = LCELL( _EQ013);
_EQ013 = a & b3 & !_LC5_C14
# a & b4 & _LC5_C14;
-- Node name is ':1515'
-- Equation name is '_LC2_B8', type is buried
_LC2_B8 = LCELL( _EQ014);
_EQ014 = a & b2 & !_LC5_C14
# a & b3 & _LC5_C14;
-- Node name is ':1521'
-- Equation name is '_LC1_B8', type is buried
_LC1_B8 = LCELL( _EQ015);
_EQ015 = a & b1 & !_LC5_C14
# a & b2 & _LC5_C14;
-- Node name is ':1527'
-- Equation name is '_LC3_B8', type is buried
_LC3_B8 = LCELL( _EQ016);
_EQ016 = a & b0 & !_LC5_C14
# a & b1 & _LC5_C14;
-- Node name is ':1532'
-- Equation name is '_LC8_B8', type is buried
_LC8_B8 = LCELL( _EQ017);
_EQ017 = a & !_LC5_C14 & _LC8_B8
# a & b0 & _LC5_C14;
Project Information c:\windows\desktop\aaaaaaa\mul8x1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = on
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = on
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,890K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -