📄 add8.rpt
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# A0 & !B0 & !CIN;
-- Node name is '|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:75' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC1_C4', type is buried
_LC1_C4 = LCELL( _EQ007);
_EQ007 = A0 & B0 & _LC3_C4
# !A0 & !B0 & _LC3_C4
# !CIN & _LC3_C4
# !A0 & B0 & CIN & !_LC3_C4
# A0 & !B0 & CIN & !_LC3_C4;
-- Node name is '|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:76' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC7_C8', type is buried
_LC7_C8 = LCELL( _EQ008);
_EQ008 = A2 & !B2 & _LC2_C4 & _LC8_C4
# !A2 & B2 & _LC2_C4 & _LC8_C4
# A2 & B2 & _LC2_C4 & !_LC8_C4
# !A2 & !B2 & _LC2_C4 & !_LC8_C4
# A2 & B2 & !_LC2_C4 & _LC8_C4
# !A2 & !B2 & !_LC2_C4 & _LC8_C4
# A2 & !B2 & !_LC2_C4 & !_LC8_C4
# !A2 & B2 & !_LC2_C4 & !_LC8_C4;
-- Node name is '|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:77' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC2_C8', type is buried
_LC2_C8 = LCELL( _EQ009);
_EQ009 = !A3 & B3 & _LC3_C8 & _LC4_C8
# A3 & !B3 & _LC3_C8 & _LC4_C8
# A3 & B3 & !_LC3_C8 & _LC4_C8
# !A3 & !B3 & !_LC3_C8 & _LC4_C8
# A3 & B3 & _LC3_C8 & !_LC4_C8
# !A3 & !B3 & _LC3_C8 & !_LC4_C8
# !A3 & B3 & !_LC3_C8 & !_LC4_C8
# A3 & !B3 & !_LC3_C8 & !_LC4_C8;
-- Node name is '|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:78' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC6_C8', type is buried
_LC6_C8 = LCELL( _EQ010);
_EQ010 = !A3 & _LC3_C8 & _LC4_C8
# A3 & !B3 & _LC4_C8
# !A3 & B3 & _LC4_C8
# !A3 & B3 & _LC3_C8
# A3 & !B3 & _LC3_C8
# A3 & B3 & !_LC3_C8
# B3 & _LC3_C8 & !_LC4_C8
# A3 & _LC3_C8 & !_LC4_C8
# A3 & B3 & !_LC4_C8;
-- Node name is '|ADD4:2|LPM_ADD_SUB:46|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_B7', type is buried
_LC2_B7 = LCELL( _EQ011);
_EQ011 = A5 & B5
# A4 & A5 & B4
# A4 & B4 & B5;
-- Node name is '|ADD4:2|LPM_ADD_SUB:46|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC5_B7', type is buried
_LC5_B7 = LCELL( _EQ012);
_EQ012 = A6 & _LC2_B7
# B6 & _LC2_B7
# A6 & B6;
-- Node name is '|ADD4:2|LPM_ADD_SUB:46|addcore:adder|:88' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC3_B7', type is buried
_LC3_B7 = LCELL( _EQ013);
_EQ013 = A4 & A5 & B4 & B5
# A5 & !B4 & !B5
# !A4 & A5 & !B5
# !A5 & !B4 & B5
# !A4 & !A5 & B5
# A4 & !A5 & B4 & !B5;
-- Node name is '|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_C8', type is buried
_LC1_C8 = LCELL( _EQ014);
_EQ014 = !A4 & B4 & _LC3_B7 & _LC6_C8
# A4 & !B4 & _LC3_B7 & _LC6_C8;
-- Node name is '|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B7', type is buried
_LC6_B7 = LCELL( _EQ015);
_EQ015 = A6 & !B6 & _LC1_C8 & !_LC2_B7
# !A6 & B6 & _LC1_C8 & !_LC2_B7
# A6 & B6 & _LC1_C8 & _LC2_B7
# !A6 & !B6 & _LC1_C8 & _LC2_B7;
-- Node name is '|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:73' from file "addcore.tdf" line 315, column 26
-- Equation name is '_LC5_C8', type is buried
_LC5_C8 = LCELL( _EQ016);
_EQ016 = A4 & B4 & _LC6_C8
# !A4 & !B4 & _LC6_C8
# !A4 & B4 & !_LC6_C8
# A4 & !B4 & !_LC6_C8;
-- Node name is '|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:75' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC8_C8', type is buried
_LC8_C8 = LCELL( _EQ017);
_EQ017 = A4 & B4 & _LC3_B7
# !A4 & !B4 & _LC3_B7
# _LC3_B7 & !_LC6_C8
# !A4 & B4 & !_LC3_B7 & _LC6_C8
# A4 & !B4 & !_LC3_B7 & _LC6_C8;
-- Node name is '|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:76' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC1_B7', type is buried
_LC1_B7 = LCELL( _EQ018);
_EQ018 = A6 & !B6 & _LC1_C8 & _LC2_B7
# !A6 & B6 & _LC1_C8 & _LC2_B7
# A6 & B6 & _LC1_C8 & !_LC2_B7
# !A6 & !B6 & _LC1_C8 & !_LC2_B7
# A6 & B6 & !_LC1_C8 & _LC2_B7
# !A6 & !B6 & !_LC1_C8 & _LC2_B7
# A6 & !B6 & !_LC1_C8 & !_LC2_B7
# !A6 & B6 & !_LC1_C8 & !_LC2_B7;
-- Node name is '|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:77' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC4_B7', type is buried
_LC4_B7 = LCELL( _EQ019);
_EQ019 = !A7 & B7 & _LC5_B7 & _LC6_B7
# A7 & !B7 & _LC5_B7 & _LC6_B7
# A7 & B7 & !_LC5_B7 & _LC6_B7
# !A7 & !B7 & !_LC5_B7 & _LC6_B7
# A7 & B7 & _LC5_B7 & !_LC6_B7
# !A7 & !B7 & _LC5_B7 & !_LC6_B7
# !A7 & B7 & !_LC5_B7 & !_LC6_B7
# A7 & !B7 & !_LC5_B7 & !_LC6_B7;
-- Node name is '|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:78' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC8_B7', type is buried
_LC8_B7 = LCELL( _EQ020);
_EQ020 = !A7 & _LC5_B7 & _LC6_B7
# A7 & !B7 & _LC6_B7
# !A7 & B7 & _LC6_B7
# !A7 & B7 & _LC5_B7
# A7 & !B7 & _LC5_B7
# A7 & B7 & !_LC5_B7
# B7 & _LC5_B7 & !_LC6_B7
# A7 & _LC5_B7 & !_LC6_B7
# A7 & B7 & !_LC6_B7;
Project Information c:\windows\desktop\tiaoshi\test8\add8.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,329K
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