📄 add8.rpt
字号:
65 - - B -- INPUT 0 0 0 2 B5
66 - - B -- INPUT 0 0 0 3 B6
67 - - B -- INPUT 0 0 0 2 B7
44 - - - -- INPUT 0 0 0 3 CIN
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\windows\desktop\tiaoshi\test8\add8.rpt
add8
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
25 - - B -- OUTPUT 0 1 0 0 COUT
8 - - - 03 OUTPUT 0 1 0 0 S0
27 - - C -- OUTPUT 0 1 0 0 S1
30 - - C -- OUTPUT 0 1 0 0 S2
28 - - C -- OUTPUT 0 1 0 0 S3
29 - - C -- OUTPUT 0 1 0 0 S4
36 - - - 07 OUTPUT 0 1 0 0 S5
21 - - B -- OUTPUT 0 1 0 0 S6
23 - - B -- OUTPUT 0 1 0 0 S7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\windows\desktop\tiaoshi\test8\add8.rpt
add8
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - C 04 OR2 4 0 0 3 |ADD4:1|LPM_ADD_SUB:46|addcore:adder|pcarry1
- 3 - C 08 OR2 2 1 0 2 |ADD4:1|LPM_ADD_SUB:46|addcore:adder|pcarry2
- 3 - C 04 OR2 4 0 0 2 |ADD4:1|LPM_ADD_SUB:46|addcore:adder|:88
- 2 - C 04 OR2 3 1 0 2 |ADD4:1|LPM_ADD_SUB:47|addcore:adder|:59
- 4 - C 08 OR2 2 2 0 2 |ADD4:1|LPM_ADD_SUB:47|addcore:adder|:63
- 6 - C 04 OR2 3 0 1 0 |ADD4:1|LPM_ADD_SUB:47|addcore:adder|:73
- 1 - C 04 OR2 3 1 1 0 |ADD4:1|LPM_ADD_SUB:47|addcore:adder|:75
- 7 - C 08 OR2 2 2 1 0 |ADD4:1|LPM_ADD_SUB:47|addcore:adder|:76
- 2 - C 08 OR2 2 2 1 0 |ADD4:1|LPM_ADD_SUB:47|addcore:adder|:77
- 6 - C 08 OR2 2 2 0 3 |ADD4:1|LPM_ADD_SUB:47|addcore:adder|:78
- 2 - B 07 OR2 4 0 0 3 |ADD4:2|LPM_ADD_SUB:46|addcore:adder|pcarry1
- 5 - B 07 OR2 2 1 0 2 |ADD4:2|LPM_ADD_SUB:46|addcore:adder|pcarry2
- 3 - B 07 OR2 4 0 0 2 |ADD4:2|LPM_ADD_SUB:46|addcore:adder|:88
- 1 - C 08 OR2 2 2 0 2 |ADD4:2|LPM_ADD_SUB:47|addcore:adder|:59
- 6 - B 07 OR2 2 2 0 2 |ADD4:2|LPM_ADD_SUB:47|addcore:adder|:63
- 5 - C 08 OR2 2 1 1 0 |ADD4:2|LPM_ADD_SUB:47|addcore:adder|:73
- 8 - C 08 OR2 2 2 1 0 |ADD4:2|LPM_ADD_SUB:47|addcore:adder|:75
- 1 - B 07 OR2 2 2 1 0 |ADD4:2|LPM_ADD_SUB:47|addcore:adder|:76
- 4 - B 07 OR2 2 2 1 0 |ADD4:2|LPM_ADD_SUB:47|addcore:adder|:77
- 8 - B 07 OR2 2 2 1 0 |ADD4:2|LPM_ADD_SUB:47|addcore:adder|:78
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\windows\desktop\tiaoshi\test8\add8.rpt
add8
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 6/ 96( 6%) 4/ 48( 8%) 0/ 48( 0%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
C: 8/ 96( 8%) 4/ 48( 8%) 0/ 48( 0%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\windows\desktop\tiaoshi\test8\add8.rpt
add8
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
A4 : INPUT;
A5 : INPUT;
A6 : INPUT;
A7 : INPUT;
B0 : INPUT;
B1 : INPUT;
B2 : INPUT;
B3 : INPUT;
B4 : INPUT;
B5 : INPUT;
B6 : INPUT;
B7 : INPUT;
CIN : INPUT;
-- Node name is 'COUT'
-- Equation name is 'COUT', type is output
COUT = _LC8_B7;
-- Node name is 'S0'
-- Equation name is 'S0', type is output
S0 = _LC6_C4;
-- Node name is 'S1'
-- Equation name is 'S1', type is output
S1 = _LC1_C4;
-- Node name is 'S2'
-- Equation name is 'S2', type is output
S2 = _LC7_C8;
-- Node name is 'S3'
-- Equation name is 'S3', type is output
S3 = _LC2_C8;
-- Node name is 'S4'
-- Equation name is 'S4', type is output
S4 = _LC5_C8;
-- Node name is 'S5'
-- Equation name is 'S5', type is output
S5 = _LC8_C8;
-- Node name is 'S6'
-- Equation name is 'S6', type is output
S6 = _LC1_B7;
-- Node name is 'S7'
-- Equation name is 'S7', type is output
S7 = _LC4_B7;
-- Node name is '|ADD4:1|LPM_ADD_SUB:46|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC8_C4', type is buried
_LC8_C4 = LCELL( _EQ001);
_EQ001 = A1 & B1
# A0 & A1 & B0
# A0 & B0 & B1;
-- Node name is '|ADD4:1|LPM_ADD_SUB:46|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_C8', type is buried
_LC3_C8 = LCELL( _EQ002);
_EQ002 = A2 & _LC8_C4
# B2 & _LC8_C4
# A2 & B2;
-- Node name is '|ADD4:1|LPM_ADD_SUB:46|addcore:adder|:88' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC3_C4', type is buried
_LC3_C4 = LCELL( _EQ003);
_EQ003 = A0 & A1 & B0 & B1
# A1 & !B0 & !B1
# !A0 & A1 & !B1
# !A1 & !B0 & B1
# !A0 & !A1 & B1
# A0 & !A1 & B0 & !B1;
-- Node name is '|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C4', type is buried
_LC2_C4 = LCELL( _EQ004);
_EQ004 = !A0 & B0 & CIN & _LC3_C4
# A0 & !B0 & CIN & _LC3_C4;
-- Node name is '|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_C8', type is buried
_LC4_C8 = LCELL( _EQ005);
_EQ005 = A2 & !B2 & _LC2_C4 & !_LC8_C4
# !A2 & B2 & _LC2_C4 & !_LC8_C4
# A2 & B2 & _LC2_C4 & _LC8_C4
# !A2 & !B2 & _LC2_C4 & _LC8_C4;
-- Node name is '|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:73' from file "addcore.tdf" line 315, column 26
-- Equation name is '_LC6_C4', type is buried
_LC6_C4 = LCELL( _EQ006);
_EQ006 = A0 & B0 & CIN
# !A0 & !B0 & CIN
# !A0 & B0 & !CIN
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -