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📄 add16.rpt

📁 几个VHDL实现的源程序及其代码
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-- Equation name is '_LC6_B5', type is buried 
_LC6_B5  = LCELL( _EQ024);
  _EQ024 = !A8 &  B8 &  _LC1_B5 &  _LC8_B5
         #  A8 & !B8 &  _LC1_B5 &  _LC8_B5;

-- Node name is '|add8:2|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_A13', type is buried 
_LC8_A13 = LCELL( _EQ025);
  _EQ025 =  A10 & !B10 & !_LC3_A13 &  _LC6_B5
         # !A10 &  B10 & !_LC3_A13 &  _LC6_B5
         #  A10 &  B10 &  _LC3_A13 &  _LC6_B5
         # !A10 & !B10 &  _LC3_A13 &  _LC6_B5;

-- Node name is '|add8:2|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:73' from file "addcore.tdf" line 315, column 26
-- Equation name is '_LC3_B5', type is buried 
_LC3_B5  = LCELL( _EQ026);
  _EQ026 = !A8 &  B8 & !_LC8_B5
         #  A8 & !B8 & !_LC8_B5
         #  A8 &  B8 &  _LC8_B5
         # !A8 & !B8 &  _LC8_B5;

-- Node name is '|add8:2|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:75' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC2_B5', type is buried 
_LC2_B5  = LCELL( _EQ027);
  _EQ027 = !A8 &  B8 & !_LC1_B5 &  _LC8_B5
         #  A8 & !B8 & !_LC1_B5 &  _LC8_B5
         #  A8 &  B8 &  _LC1_B5
         # !A8 & !B8 &  _LC1_B5
         #  _LC1_B5 & !_LC8_B5;

-- Node name is '|add8:2|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:76' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC4_A13', type is buried 
_LC4_A13 = LCELL( _EQ028);
  _EQ028 =  A10 & !B10 & !_LC3_A13 & !_LC6_B5
         # !A10 &  B10 & !_LC3_A13 & !_LC6_B5
         #  A10 &  B10 &  _LC3_A13 & !_LC6_B5
         # !A10 & !B10 &  _LC3_A13 & !_LC6_B5
         #  A10 & !B10 &  _LC3_A13 &  _LC6_B5
         # !A10 &  B10 &  _LC3_A13 &  _LC6_B5
         #  A10 &  B10 & !_LC3_A13 &  _LC6_B5
         # !A10 & !B10 & !_LC3_A13 &  _LC6_B5;

-- Node name is '|add8:2|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:77' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC5_A13', type is buried 
_LC5_A13 = LCELL( _EQ029);
  _EQ029 = !A11 &  B11 & !_LC6_A13 & !_LC8_A13
         #  A11 & !B11 & !_LC6_A13 & !_LC8_A13
         #  A11 &  B11 &  _LC6_A13 & !_LC8_A13
         # !A11 & !B11 &  _LC6_A13 & !_LC8_A13
         # !A11 &  B11 &  _LC6_A13 &  _LC8_A13
         #  A11 & !B11 &  _LC6_A13 &  _LC8_A13
         #  A11 &  B11 & !_LC6_A13 &  _LC8_A13
         # !A11 & !B11 & !_LC6_A13 &  _LC8_A13;

-- Node name is '|add8:2|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:78' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC1_A13', type is buried 
_LC1_A13 = LCELL( _EQ030);
  _EQ030 = !A11 &  _LC6_A13 &  _LC8_A13
         #  A11 & !B11 &  _LC8_A13
         # !A11 &  B11 &  _LC8_A13
         # !A11 &  B11 &  _LC6_A13
         #  A11 & !B11 &  _LC6_A13
         #  A11 &  B11 & !_LC6_A13
         #  B11 &  _LC6_A13 & !_LC8_A13
         #  A11 &  _LC6_A13 & !_LC8_A13
         #  A11 &  B11 & !_LC8_A13;

-- Node name is '|add8:2|ADD4:2|LPM_ADD_SUB:46|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_A20', type is buried 
_LC4_A20 = LCELL( _EQ031);
  _EQ031 =  A13 &  B13
         #  A12 &  B12 &  B13
         #  A12 &  A13 &  B12;

-- Node name is '|add8:2|ADD4:2|LPM_ADD_SUB:46|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC5_A20', type is buried 
_LC5_A20 = LCELL( _EQ032);
  _EQ032 =  A14 &  _LC4_A20
         #  B14 &  _LC4_A20
         #  A14 &  B14;

-- Node name is '|add8:2|ADD4:2|LPM_ADD_SUB:46|addcore:adder|:88' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC1_A20', type is buried 
_LC1_A20 = LCELL( _EQ033);
  _EQ033 =  A12 & !A13 &  B12 & !B13
         # !A13 & !B12 &  B13
         # !A12 & !A13 &  B13
         #  A12 &  A13 &  B12 &  B13
         #  A13 & !B12 & !B13
         # !A12 &  A13 & !B13;

-- Node name is '|add8:2|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A20', type is buried 
_LC6_A20 = LCELL( _EQ034);
  _EQ034 = !A12 &  B12 &  _LC1_A13 &  _LC1_A20
         #  A12 & !B12 &  _LC1_A13 &  _LC1_A20;

-- Node name is '|add8:2|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_A20', type is buried 
_LC8_A20 = LCELL( _EQ035);
  _EQ035 =  A14 & !B14 & !_LC4_A20 &  _LC6_A20
         # !A14 &  B14 & !_LC4_A20 &  _LC6_A20
         #  A14 &  B14 &  _LC4_A20 &  _LC6_A20
         # !A14 & !B14 &  _LC4_A20 &  _LC6_A20;

-- Node name is '|add8:2|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:73' from file "addcore.tdf" line 315, column 26
-- Equation name is '_LC7_A13', type is buried 
_LC7_A13 = LCELL( _EQ036);
  _EQ036 = !A12 &  B12 & !_LC1_A13
         #  A12 & !B12 & !_LC1_A13
         #  A12 &  B12 &  _LC1_A13
         # !A12 & !B12 &  _LC1_A13;

-- Node name is '|add8:2|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:75' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC2_A13', type is buried 
_LC2_A13 = LCELL( _EQ037);
  _EQ037 = !A12 &  B12 &  _LC1_A13 & !_LC1_A20
         #  A12 & !B12 &  _LC1_A13 & !_LC1_A20
         #  A12 &  B12 &  _LC1_A20
         # !A12 & !B12 &  _LC1_A20
         # !_LC1_A13 &  _LC1_A20;

-- Node name is '|add8:2|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:76' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC3_A20', type is buried 
_LC3_A20 = LCELL( _EQ038);
  _EQ038 =  A14 & !B14 & !_LC4_A20 & !_LC6_A20
         # !A14 &  B14 & !_LC4_A20 & !_LC6_A20
         #  A14 &  B14 &  _LC4_A20 & !_LC6_A20
         # !A14 & !B14 &  _LC4_A20 & !_LC6_A20
         #  A14 & !B14 &  _LC4_A20 &  _LC6_A20
         # !A14 &  B14 &  _LC4_A20 &  _LC6_A20
         #  A14 &  B14 & !_LC4_A20 &  _LC6_A20
         # !A14 & !B14 & !_LC4_A20 &  _LC6_A20;

-- Node name is '|add8:2|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:77' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC2_A20', type is buried 
_LC2_A20 = LCELL( _EQ039);
  _EQ039 = !A15 &  B15 & !_LC5_A20 & !_LC8_A20
         #  A15 & !B15 & !_LC5_A20 & !_LC8_A20
         #  A15 &  B15 &  _LC5_A20 & !_LC8_A20
         # !A15 & !B15 &  _LC5_A20 & !_LC8_A20
         # !A15 &  B15 &  _LC5_A20 &  _LC8_A20
         #  A15 & !B15 &  _LC5_A20 &  _LC8_A20
         #  A15 &  B15 & !_LC5_A20 &  _LC8_A20
         # !A15 & !B15 & !_LC5_A20 &  _LC8_A20;

-- Node name is '|add8:2|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:78' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC7_A20', type is buried 
_LC7_A20 = LCELL( _EQ040);
  _EQ040 = !A15 &  _LC5_A20 &  _LC8_A20
         #  A15 & !B15 &  _LC8_A20
         # !A15 &  B15 &  _LC8_A20
         # !A15 &  B15 &  _LC5_A20
         #  A15 & !B15 &  _LC5_A20
         #  A15 &  B15 & !_LC5_A20
         #  B15 &  _LC5_A20 & !_LC8_A20
         #  A15 &  _LC5_A20 & !_LC8_A20
         #  A15 &  B15 & !_LC8_A20;



Project Information                 c:\windows\desktop\tiaoshi\test8\add16.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 15,894K

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