📄 add16.rpt
字号:
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
62 - - C -- INPUT 0 0 0 5 A0
61 - - C -- INPUT 0 0 0 2 A1
59 - - C -- INPUT 0 0 0 3 A2
24 - - B -- INPUT 0 0 0 2 A3
39 - - - 11 INPUT 0 0 0 5 A4
65 - - B -- INPUT 0 0 0 2 A5
3 - - - 12 INPUT 0 0 0 3 A6
66 - - B -- INPUT 0 0 0 2 A7
43 - - - -- INPUT 0 0 0 5 A8
44 - - - -- INPUT 0 0 0 2 A9
80 - - - 23 INPUT 0 0 0 3 A10
54 - - - 21 INPUT 0 0 0 2 A11
42 - - - -- INPUT 0 0 0 5 A12
17 - - A -- INPUT 0 0 0 2 A13
18 - - A -- INPUT 0 0 0 3 A14
19 - - A -- INPUT 0 0 0 2 A15
60 - - C -- INPUT 0 0 0 5 B0
37 - - - 09 INPUT 0 0 0 2 B1
27 - - C -- INPUT 0 0 0 3 B2
67 - - B -- INPUT 0 0 0 2 B3
7 - - - 03 INPUT 0 0 0 5 B4
64 - - B -- INPUT 0 0 0 2 B5
9 - - - 02 INPUT 0 0 0 3 B6
36 - - - 07 INPUT 0 0 0 2 B7
1 - - - -- INPUT 0 0 0 5 B8
84 - - - -- INPUT 0 0 0 2 B9
78 - - - 24 INPUT 0 0 0 3 B10
73 - - A -- INPUT 0 0 0 2 B11
2 - - - -- INPUT 0 0 0 5 B12
16 - - A -- INPUT 0 0 0 2 B13
49 - - - 16 INPUT 0 0 0 3 B14
72 - - A -- INPUT 0 0 0 2 B15
58 - - C -- INPUT 0 0 0 3 cin
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\windows\desktop\tiaoshi\test8\add16.rpt
add16
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
69 - - A -- OUTPUT 0 1 0 0 cout
28 - - C -- OUTPUT 0 1 0 0 s0
30 - - C -- OUTPUT 0 1 0 0 s1
29 - - C -- OUTPUT 0 1 0 0 s2
8 - - - 03 OUTPUT 0 1 0 0 s3
25 - - B -- OUTPUT 0 1 0 0 s4
21 - - B -- OUTPUT 0 1 0 0 s5
6 - - - 04 OUTPUT 0 1 0 0 s6
23 - - B -- OUTPUT 0 1 0 0 s7
35 - - - 06 OUTPUT 0 1 0 0 s8
22 - - B -- OUTPUT 0 1 0 0 s9
71 - - A -- OUTPUT 0 1 0 0 s10
70 - - A -- OUTPUT 0 1 0 0 s11
83 - - - 13 OUTPUT 0 1 0 0 s12
47 - - - 14 OUTPUT 0 1 0 0 s13
53 - - - 20 OUTPUT 0 1 0 0 s14
52 - - - 19 OUTPUT 0 1 0 0 s15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\windows\desktop\tiaoshi\test8\add16.rpt
add16
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - C 03 OR2 4 0 0 3 |add8:1|ADD4:1|LPM_ADD_SUB:46|addcore:adder|pcarry1
- 2 - C 03 OR2 2 1 0 2 |add8:1|ADD4:1|LPM_ADD_SUB:46|addcore:adder|pcarry2
- 6 - C 03 OR2 4 0 0 2 |add8:1|ADD4:1|LPM_ADD_SUB:46|addcore:adder|:88
- 8 - C 03 OR2 3 1 0 2 |add8:1|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:59
- 1 - C 03 OR2 2 2 0 2 |add8:1|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:63
- 3 - C 03 OR2 3 0 1 0 |add8:1|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:73
- 7 - C 03 OR2 3 1 1 0 |add8:1|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:75
- 5 - C 03 OR2 2 2 1 0 |add8:1|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:76
- 4 - B 04 OR2 2 2 1 0 |add8:1|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:77
- 7 - B 04 OR2 2 2 0 3 |add8:1|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:78
- 2 - B 04 OR2 4 0 0 3 |add8:1|ADD4:2|LPM_ADD_SUB:46|addcore:adder|pcarry1
- 5 - B 05 OR2 2 1 0 2 |add8:1|ADD4:2|LPM_ADD_SUB:46|addcore:adder|pcarry2
- 5 - B 04 OR2 4 0 0 2 |add8:1|ADD4:2|LPM_ADD_SUB:46|addcore:adder|:88
- 3 - B 04 OR2 2 2 0 2 |add8:1|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:59
- 7 - B 05 OR2 2 2 0 2 |add8:1|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:63
- 8 - B 04 OR2 2 1 1 0 |add8:1|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:73
- 1 - B 04 OR2 2 2 1 0 |add8:1|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:75
- 6 - B 04 OR2 2 2 1 0 |add8:1|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:76
- 4 - B 05 OR2 2 2 1 0 |add8:1|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:77
- 8 - B 05 OR2 2 2 0 3 |add8:1|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:78
- 3 - A 13 OR2 4 0 0 3 |add8:2|ADD4:1|LPM_ADD_SUB:46|addcore:adder|pcarry1
- 6 - A 13 OR2 2 1 0 2 |add8:2|ADD4:1|LPM_ADD_SUB:46|addcore:adder|pcarry2
- 1 - B 05 OR2 4 0 0 2 |add8:2|ADD4:1|LPM_ADD_SUB:46|addcore:adder|:88
- 6 - B 05 OR2 2 2 0 2 |add8:2|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:59
- 8 - A 13 OR2 2 2 0 2 |add8:2|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:63
- 3 - B 05 OR2 2 1 1 0 |add8:2|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:73
- 2 - B 05 OR2 2 2 1 0 |add8:2|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:75
- 4 - A 13 OR2 2 2 1 0 |add8:2|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:76
- 5 - A 13 OR2 2 2 1 0 |add8:2|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:77
- 1 - A 13 OR2 2 2 0 3 |add8:2|ADD4:1|LPM_ADD_SUB:47|addcore:adder|:78
- 4 - A 20 OR2 4 0 0 3 |add8:2|ADD4:2|LPM_ADD_SUB:46|addcore:adder|pcarry1
- 5 - A 20 OR2 2 1 0 2 |add8:2|ADD4:2|LPM_ADD_SUB:46|addcore:adder|pcarry2
- 1 - A 20 OR2 4 0 0 2 |add8:2|ADD4:2|LPM_ADD_SUB:46|addcore:adder|:88
- 6 - A 20 OR2 2 2 0 2 |add8:2|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:59
- 8 - A 20 OR2 2 2 0 2 |add8:2|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:63
- 7 - A 13 OR2 2 1 1 0 |add8:2|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:73
- 2 - A 13 OR2 2 2 1 0 |add8:2|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:75
- 3 - A 20 OR2 2 2 1 0 |add8:2|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:76
- 2 - A 20 OR2 2 2 1 0 |add8:2|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:77
- 7 - A 20 OR2 2 2 1 0 |add8:2|ADD4:2|LPM_ADD_SUB:47|addcore:adder|:78
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\windows\desktop\tiaoshi\test8\add16.rpt
add16
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 7/ 96( 7%) 0/ 48( 0%) 9/ 48( 18%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
B: 8/ 96( 8%) 10/ 48( 20%) 0/ 48( 0%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
C: 7/ 96( 7%) 3/ 48( 6%) 0/ 48( 0%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 4/24( 16%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\windows\desktop\tiaoshi\test8\add16.rpt
add16
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
A4 : INPUT;
A5 : INPUT;
A6 : INPUT;
A7 : INPUT;
A8 : INPUT;
A9 : INPUT;
A10 : INPUT;
A11 : INPUT;
A12 : INPUT;
A13 : INPUT;
A14 : INPUT;
A15 : INPUT;
B0 : INPUT;
B1 : INPUT;
B2 : INPUT;
B3 : INPUT;
B4 : INPUT;
B5 : INPUT;
B6 : INPUT;
B7 : INPUT;
B8 : INPUT;
B9 : INPUT;
B10 : INPUT;
B11 : INPUT;
B12 : INPUT;
B13 : INPUT;
B14 : INPUT;
B15 : INPUT;
cin : INPUT;
-- Node name is 'cout'
-- Equation name is 'cout', type is output
cout = _LC7_A20;
-- Node name is 's0'
-- Equation name is 's0', type is output
s0 = _LC3_C3;
-- Node name is 's1'
-- Equation name is 's1', type is output
s1 = _LC7_C3;
-- Node name is 's2'
-- Equation name is 's2', type is output
s2 = _LC5_C3;
-- Node name is 's3'
-- Equation name is 's3', type is output
s3 = _LC4_B4;
-- Node name is 's4'
-- Equation name is 's4', type is output
s4 = _LC8_B4;
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