sreg8b.vhd

来自「几个VHDL实现的源程序及其代码」· VHDL 代码 · 共 27 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY SREG8B IS               
PORT(
CLK: IN STD_LOGIC;
LOAD: IN STD_LOGIC;
DIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
QB: OUT STD_LOGIC);
END SREG8B;

ARCHITECTURE BEHAV OF SREG8B IS
SIGNAL REG8 : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(CLK,LOAD)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF LOAD='1' THEN
REG8<=DIN;
ELSE
REG8(6 DOWNTO 0)<=REG8(7 DOWNTO 1);  
END IF;
END IF;
END PROCESS;
QB<=REG8(0);                    
END BEHAV;