qiangdaqi.rpt

几个VHDL实现的源程序及其代码

+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:c:\windows\desktop\edaplay\digital\test18\qiangdaqi.rpt
qiangdaqi8

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'G':

                 Logic cells placed in LAB 'G'
        +------- LC105 sel0
        | +----- LC107 sel1
        | | +--- LC109 sel2
        | | | +- LC104 SPEAK
        | | | | 
        | | | |   Other LABs fed by signals
        | | | |   that feed LAB 'G'
LC      | | | | | A B C D E F G H |     Logic cells that feed LAB 'G':

Pin
83   -> - - - - | - - - - - - - * | <-- CLK
1    -> - - - - | - - - - - - - * | <-- CTL
LC115-> - - - * | - - - - - - * * | <-- DA1
LC117-> - - - * | - - - - - - * * | <-- DA2
LC118-> - - - * | - - - - - - * * | <-- DA3
LC120-> - - - * | - - - - - - * * | <-- DA4
LC123-> - - - * | - - - - - - * * | <-- DA5
LC125-> - - - * | - - - - - - * * | <-- DA6
LC126-> - - - * | - - - - - - * * | <-- DA7
LC128-> - - - * | - - - - - - * * | <-- DA8


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:c:\windows\desktop\edaplay\digital\test18\qiangdaqi.rpt
qiangdaqi8

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                         Logic cells placed in LAB 'H'
        +--------------- LC115 DA1
        | +------------- LC117 DA2
        | | +----------- LC118 DA3
        | | | +--------- LC120 DA4
        | | | | +------- LC123 DA5
        | | | | | +----- LC125 DA6
        | | | | | | +--- LC126 DA7
        | | | | | | | +- LC128 DA8
        | | | | | | | | 
        | | | | | | | |   Other LABs fed by signals
        | | | | | | | |   that feed LAB 'H'
LC      | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC115-> * * * * * * * * | - - - - - - * * | <-- DA1
LC117-> * * * * * * * * | - - - - - - * * | <-- DA2
LC118-> * * * * * * * * | - - - - - - * * | <-- DA3
LC120-> * * * * * * * * | - - - - - - * * | <-- DA4
LC123-> * * * * * * * * | - - - - - - * * | <-- DA5
LC125-> * * * * * * * * | - - - - - - * * | <-- DA6
LC126-> * * * * * * * * | - - - - - - * * | <-- DA7
LC128-> * * * * * * * * | - - - - - - * * | <-- DA8

Pin
83   -> * * * * * * * * | - - - - - - - * | <-- CLK
1    -> * * * * * * * * | - - - - - - - * | <-- CTL
4    -> * - - - - - - - | - - - - - - - * | <-- k1
5    -> - * - - - - - - | - - - - - - - * | <-- k2
6    -> - - * - - - - - | - - - - - - - * | <-- k3
8    -> - - - * - - - - | - - - - - - - * | <-- k4
9    -> - - - - * - - - | - - - - - - - * | <-- K5
10   -> - - - - - * - - | - - - - - - - * | <-- k6
11   -> - - - - - - * - | - - - - - - - * | <-- k7
12   -> - - - - - - - * | - - - - - - - * | <-- k8


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:c:\windows\desktop\edaplay\digital\test18\qiangdaqi.rpt
qiangdaqi8

** EQUATIONS **

CLK      : INPUT;
CTL      : INPUT;
k1       : INPUT;
k2       : INPUT;
k3       : INPUT;
k4       : INPUT;
K5       : INPUT;
k6       : INPUT;
k7       : INPUT;
k8       : INPUT;

-- Node name is 'DA1' = ':8' 
-- Equation name is 'DA1', type is output 
DA1      = _LC115~NOT;
_LC115~NOT = DFFE(!k1 $  VCC,  _EQ001,  VCC,  CTL,  VCC);
  _EQ001 =  CLK &  DA1 &  DA2 &  DA3 &  DA4 &  DA5 &  DA6 &  DA7 &  DA8;

-- Node name is 'DA2' = ':10' 
-- Equation name is 'DA2', type is output 
DA2      = _LC117~NOT;
_LC117~NOT = DFFE(!k2 $  VCC,  _EQ002,  VCC,  CTL,  VCC);
  _EQ002 =  CLK &  DA1 &  DA2 &  DA3 &  DA4 &  DA5 &  DA6 &  DA7 &  DA8;

-- Node name is 'DA3' = ':12' 
-- Equation name is 'DA3', type is output 
DA3      = _LC118~NOT;
_LC118~NOT = DFFE(!k3 $  VCC,  _EQ003,  VCC,  CTL,  VCC);
  _EQ003 =  CLK &  DA1 &  DA2 &  DA3 &  DA4 &  DA5 &  DA6 &  DA7 &  DA8;

-- Node name is 'DA4' = ':11' 
-- Equation name is 'DA4', type is output 
DA4      = _LC120~NOT;
_LC120~NOT = DFFE(!k4 $  VCC,  _EQ004,  VCC,  CTL,  VCC);
  _EQ004 =  CLK &  DA1 &  DA2 &  DA3 &  DA4 &  DA5 &  DA6 &  DA7 &  DA8;

-- Node name is 'DA5' = ':16' 
-- Equation name is 'DA5', type is output 
DA5      = _LC123~NOT;
_LC123~NOT = DFFE(!K5 $  VCC,  _EQ005,  VCC,  CTL,  VCC);
  _EQ005 =  CLK &  DA1 &  DA2 &  DA3 &  DA4 &  DA5 &  DA6 &  DA7 &  DA8;

-- Node name is 'DA6' = ':15' 
-- Equation name is 'DA6', type is output 
DA6      = _LC125~NOT;
_LC125~NOT = DFFE(!k6 $  VCC,  _EQ006,  VCC,  CTL,  VCC);
  _EQ006 =  CLK &  DA1 &  DA2 &  DA3 &  DA4 &  DA5 &  DA6 &  DA7 &  DA8;

-- Node name is 'DA7' = ':14' 
-- Equation name is 'DA7', type is output 
DA7      = _LC126~NOT;
_LC126~NOT = DFFE(!k7 $  VCC,  _EQ007,  VCC,  CTL,  VCC);
  _EQ007 =  CLK &  DA1 &  DA2 &  DA3 &  DA4 &  DA5 &  DA6 &  DA7 &  DA8;

-- Node name is 'DA8' = ':13' 
-- Equation name is 'DA8', type is output 
DA8      = _LC128~NOT;
_LC128~NOT = DFFE(!k8 $  VCC,  _EQ008,  VCC,  CTL,  VCC);
  _EQ008 =  CLK &  DA1 &  DA2 &  DA3 &  DA4 &  DA5 &  DA6 &  DA7 &  DA8;

-- Node name is 'sel0' 
-- Equation name is 'sel0', location is LC105, type is output.
 sel0    = LCELL( GND $  GND);

-- Node name is 'sel1' 
-- Equation name is 'sel1', location is LC107, type is output.
 sel1    = LCELL( GND $  GND);

-- Node name is 'sel2' 
-- Equation name is 'sel2', location is LC109, type is output.
 sel2    = LCELL( GND $  GND);

-- Node name is 'SPEAK' 
-- Equation name is 'SPEAK', location is LC104, type is output.
 SPEAK   = LCELL( _EQ009 $  VCC);
  _EQ009 = !DA1 & !DA2 & !DA3 & !DA4 & !DA5 & !DA6 & !DA7 & !DA8;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information    c:\windows\desktop\edaplay\digital\test18\qiangdaqi.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off
ADT PALACE Compilation                    = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,250K