📄 spk.rpt
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** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 9/ 96( 9%) 0/ 48( 0%) 8/ 48( 16%) 8/16( 50%) 1/16( 6%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\windows\desktop\edaplay\digital\test18\spk.rpt
spk
** EQUATIONS **
k1 : INPUT;
k2 : INPUT;
k3 : INPUT;
k4 : INPUT;
k5 : INPUT;
k6 : INPUT;
k7 : INPUT;
k8 : INPUT;
q1 : INPUT;
q2 : INPUT;
q3 : INPUT;
q4 : INPUT;
q5 : INPUT;
q6 : INPUT;
q7 : INPUT;
q8 : INPUT;
-- Node name is 'spk'
-- Equation name is 'spk', type is output
spk = _LC1_A24;
-- Node name is '~162~1'
-- Equation name is '~162~1', location is LC3_A13, type is buried.
-- synthesized logic cell
_LC3_A13 = LCELL( _EQ001);
_EQ001 = !k4 & !q6 & !q7;
-- Node name is '~162~2'
-- Equation name is '~162~2', location is LC1_A13, type is buried.
-- synthesized logic cell
_LC1_A13 = LCELL( _EQ002);
_EQ002 = !k1 & k7 & _LC3_A13 & q1;
-- Node name is '~167~1'
-- Equation name is '~167~1', location is LC4_A17, type is buried.
-- synthesized logic cell
_LC4_A17 = LCELL( _EQ003);
_EQ003 = k8 & _LC3_A17 & q5 & q6;
-- Node name is '~198~1'
-- Equation name is '~198~1', location is LC2_A17, type is buried.
-- synthesized logic cell
_LC2_A17 = LCELL( _EQ004);
_EQ004 = !k2 & !k3 & !k8 & q3;
-- Node name is '~198~2'
-- Equation name is '~198~2', location is LC7_A24, type is buried.
-- synthesized logic cell
_LC7_A24 = LCELL( _EQ005);
_EQ005 = k6 & _LC2_A17 & _LC3_A24 & q5;
-- Node name is '~234~1'
-- Equation name is '~234~1', location is LC3_A24, type is buried.
-- synthesized logic cell
_LC3_A24 = LCELL( _EQ006);
_EQ006 = !q2 & q6;
-- Node name is '~381~1'
-- Equation name is '~381~1', location is LC2_A13, type is buried.
-- synthesized logic cell
_LC2_A13 = LCELL( _EQ007);
_EQ007 = k1 & !k4 & !q6 & !q7
# !k1 & k4 & q6 & q7;
-- Node name is '~381~2'
-- Equation name is '~381~2', location is LC1_A16, type is buried.
-- synthesized logic cell
_LC1_A16 = LCELL( _EQ008);
_EQ008 = _LC1_A13
# !k7 & _LC2_A13 & !q1;
-- Node name is '~381~3'
-- Equation name is '~381~3', location is LC2_A24, type is buried.
-- synthesized logic cell
_LC2_A24 = LCELL( _EQ009);
_EQ009 = !k5 & _LC1_A16 & q2 & !q4;
-- Node name is '~381~4'
-- Equation name is '~381~4', location is LC4_A13, type is buried.
-- synthesized logic cell
_LC4_A13 = LCELL( _EQ010);
_EQ010 = !k4 & q4 & q7;
-- Node name is '~381~5'
-- Equation name is '~381~5', location is LC8_A13, type is buried.
-- synthesized logic cell
_LC8_A13 = LCELL( _EQ011);
_EQ011 = !k1 & !k7 & _LC4_A13 & q1;
-- Node name is '~381~6'
-- Equation name is '~381~6', location is LC4_A24, type is buried.
-- synthesized logic cell
_LC4_A24 = LCELL( _EQ012);
_EQ012 = _LC2_A24
# k5 & _LC3_A24 & _LC8_A13;
-- Node name is '~381~7'
-- Equation name is '~381~7', location is LC5_A24, type is buried.
-- synthesized logic cell
_LC5_A24 = LCELL( _EQ013);
_EQ013 = !k6 & _LC2_A17 & _LC4_A24 & !q5;
-- Node name is '~381~8'
-- Equation name is '~381~8', location is LC6_A24, type is buried.
-- synthesized logic cell
_LC6_A24 = LCELL( _EQ014);
_EQ014 = !k5 & _LC8_A13;
-- Node name is '~381~9'
-- Equation name is '~381~9', location is LC3_A17, type is buried.
-- synthesized logic cell
_LC3_A17 = LCELL( _EQ015);
_EQ015 = !k2 & !k3 & q3;
-- Node name is '~381~10'
-- Equation name is '~381~10', location is LC5_A17, type is buried.
-- synthesized logic cell
_LC5_A17 = LCELL( _EQ016);
_EQ016 = k2 & !k3 & !q3 & q5
# !k2 & k3 & q3 & !q5;
-- Node name is '~381~11'
-- Equation name is '~381~11', location is LC1_A17, type is buried.
-- synthesized logic cell
_LC1_A17 = LCELL( _EQ017);
_EQ017 = _LC4_A17
# !k8 & _LC5_A17 & !q6;
-- Node name is '~381~12'
-- Equation name is '~381~12', location is LC8_A24, type is buried.
-- synthesized logic cell
_LC8_A24 = LCELL( _EQ018);
_EQ018 = _LC7_A24
# !k6 & _LC1_A17 & q2;
-- Node name is ':381'
-- Equation name is '_LC1_A24', type is buried
_LC1_A24 = LCELL( _EQ019);
_EQ019 = _LC5_A24 & !q8
# _LC6_A24 & _LC8_A24 & !q8;
Project Information c:\windows\desktop\edaplay\digital\test18\spk.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,340K
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