spk.vhd

几个VHDL实现的源程序及其代码

library ieee;
use ieee.std_logic_1164.all;

entity spk is
port(
q: in std_logic_vector(8 downto 1);
k: in std_logic_vector(8 downto 1);
spk : out std_logic);
end spk;

architecture behav of spk is
signal data : std_logic_vector(15 downto 0);
begin
data<=q&k;
process(q,k)
begin
case data is
when "0000011000000001"=>spk<='1';
when "0101101100000010"=>spk<='1';
when "0100111100000100"=>spk<='1';
when "0110011000001000"=>spk<='1';
when "0110110100010000"=>spk<='1';
when "0111110100100000"=>spk<='1';
when "0000011101000000"=>spk<='1';
when "0111111110000000"=>spk<='1';
when others=>spk<='0';
end case;
end process;
end behav;