hb1.rpt

几个VHDL实现的源程序及其代码


Device-Specific Information: c:\windows\desktop\edaplay\digital\test18\hb1.rpt
hb1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                         Logic cells placed in LAB 'H'
        +--------------- LC120 q1
        | +------------- LC115 q2
        | | +----------- LC117 q3
        | | | +--------- LC118 q4
        | | | | +------- LC123 q5
        | | | | | +----- LC125 q6
        | | | | | | +--- LC128 q7
        | | | | | | | +- LC126 q8
        | | | | | | | | 
        | | | | | | | |   Other LABs fed by signals
        | | | | | | | |   that feed LAB 'H'
LC      | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':

Pin
12   -> * * * * * * * - | - - - - - - - * | <-- d1
4    -> * * * * * * * - | - - - - - - - * | <-- d2
5    -> * * * * * * * - | - - - - - - - * | <-- d3
8    -> * * * * * * * - | - - - - - - - * | <-- d4
6    -> * * * * * * * - | - - - - - - - * | <-- d5
9    -> * * * * * * * - | - - - - - - - * | <-- d6
10   -> * * * * * * * - | - - - - - - - * | <-- d7
11   -> * * * * * * * - | - - - - - - - * | <-- d8


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information: c:\windows\desktop\edaplay\digital\test18\hb1.rpt
hb1

** EQUATIONS **

d1       : INPUT;
d2       : INPUT;
d3       : INPUT;
d4       : INPUT;
d5       : INPUT;
d6       : INPUT;
d7       : INPUT;
d8       : INPUT;

-- Node name is 'q1' 
-- Equation name is 'q1', location is LC120, type is output.
 q1      = LCELL( _EQ001 $  VCC);
  _EQ001 =  _X001 &  _X002 &  _X003 &  _X004 &  _X005 &  _X006;
  _X001  = EXP(!d1 & !d2 &  d3 & !d4 & !d5 & !d6 & !d7 & !d8);
  _X002  = EXP( d1 & !d2 & !d3 & !d4 & !d5 & !d6 & !d7 & !d8);
  _X003  = EXP(!d1 & !d2 & !d3 &  d4 & !d5 & !d6 & !d7 & !d8);
  _X004  = EXP(!d1 & !d2 & !d3 & !d4 & !d5 &  d6 & !d7 & !d8);
  _X005  = EXP(!d1 & !d2 & !d3 & !d4 & !d5 & !d6 &  d7 & !d8);
  _X006  = EXP(!d1 &  d2 & !d3 & !d4 & !d5 & !d6 & !d7 & !d8);

-- Node name is 'q2' 
-- Equation name is 'q2', location is LC115, type is output.
 q2      = LCELL( _EQ002 $  VCC);
  _EQ002 =  _X002 &  _X004 &  _X005 &  _X006 &  _X007 &  _X008;
  _X002  = EXP( d1 & !d2 & !d3 & !d4 & !d5 & !d6 & !d7 & !d8);
  _X004  = EXP(!d1 & !d2 & !d3 & !d4 & !d5 &  d6 & !d7 & !d8);
  _X005  = EXP(!d1 & !d2 & !d3 & !d4 & !d5 & !d6 &  d7 & !d8);
  _X006  = EXP(!d1 &  d2 & !d3 & !d4 & !d5 & !d6 & !d7 & !d8);
  _X007  = EXP(!d1 & !d2 & !d3 & !d4 &  d5 & !d6 & !d7 & !d8);
  _X008  = EXP(!d1 & !d2 & !d3 & !d4 & !d5 & !d6 & !d7 &  d8);

-- Node name is 'q3' 
-- Equation name is 'q3', location is LC117, type is output.
 q3      = LCELL( _EQ003 $  VCC);
  _EQ003 =  _X001 &  _X002 &  _X003 &  _X004 &  _X006 &  _X007 &  _X008;
  _X001  = EXP(!d1 & !d2 &  d3 & !d4 & !d5 & !d6 & !d7 & !d8);
  _X002  = EXP( d1 & !d2 & !d3 & !d4 & !d5 & !d6 & !d7 & !d8);
  _X003  = EXP(!d1 & !d2 & !d3 &  d4 & !d5 & !d6 & !d7 & !d8);
  _X004  = EXP(!d1 & !d2 & !d3 & !d4 & !d5 &  d6 & !d7 & !d8);
  _X006  = EXP(!d1 &  d2 & !d3 & !d4 & !d5 & !d6 & !d7 & !d8);
  _X007  = EXP(!d1 & !d2 & !d3 & !d4 &  d5 & !d6 & !d7 & !d8);
  _X008  = EXP(!d1 & !d2 & !d3 & !d4 & !d5 & !d6 & !d7 &  d8);

-- Node name is 'q4' 
-- Equation name is 'q4', location is LC118, type is output.
 q4      = LCELL( _EQ004 $  GND);
  _EQ004 =  d1 & !d2 & !d3 & !d4 & !d5 & !d6 & !d7 & !d8
         # !d1 & !d2 &  d3 & !d4 & !d5 & !d6 & !d7 & !d8
         # !d1 & !d2 & !d3 &  d4 & !d5 & !d6 & !d7 & !d8
         # !d1 & !d2 & !d3 & !d4 & !d5 &  d6 & !d7 & !d8
         # !d1 & !d2 & !d3 & !d4 & !d5 & !d6 &  d7 & !d8;

-- Node name is 'q5' 
-- Equation name is 'q5', location is LC123, type is output.
 q5      = LCELL( _EQ005 $  GND);
  _EQ005 =  d1 & !d2 & !d3 & !d4 & !d5 & !d6 & !d7 & !d8
         # !d1 & !d2 &  d3 & !d4 & !d5 & !d6 & !d7 & !d8
         # !d1 & !d2 & !d3 & !d4 & !d5 & !d6 &  d7 & !d8;

-- Node name is 'q6' 
-- Equation name is 'q6', location is LC125, type is output.
 q6      = LCELL( _EQ006 $  GND);
  _EQ006 =  d1 & !d2 & !d3 & !d4 & !d5 & !d6 & !d7 & !d8
         # !d1 & !d2 &  d3 & !d4 & !d5 & !d6 & !d7 & !d8
         # !d1 & !d2 & !d3 &  d4 & !d5 & !d6 & !d7 & !d8
         # !d1 & !d2 & !d3 & !d4 &  d5 & !d6 & !d7 & !d8;

-- Node name is 'q7' 
-- Equation name is 'q7', location is LC128, type is output.
 q7      = LCELL( _EQ007 $  VCC);
  _EQ007 =  _X001 &  _X002 &  _X003 &  _X004 &  _X005 &  _X007;
  _X001  = EXP(!d1 & !d2 &  d3 & !d4 & !d5 & !d6 & !d7 & !d8);
  _X002  = EXP( d1 & !d2 & !d3 & !d4 & !d5 & !d6 & !d7 & !d8);
  _X003  = EXP(!d1 & !d2 & !d3 &  d4 & !d5 & !d6 & !d7 & !d8);
  _X004  = EXP(!d1 & !d2 & !d3 & !d4 & !d5 &  d6 & !d7 & !d8);
  _X005  = EXP(!d1 & !d2 & !d3 & !d4 & !d5 & !d6 &  d7 & !d8);
  _X007  = EXP(!d1 & !d2 & !d3 & !d4 &  d5 & !d6 & !d7 & !d8);

-- Node name is 'q8' 
-- Equation name is 'q8', location is LC126, type is output.
 q8      = LCELL( VCC $  VCC);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information          c:\windows\desktop\edaplay\digital\test18\hb1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off
ADT PALACE Compilation                    = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,317K