hb1.vhd

几个VHDL实现的源程序及其代码

library ieee;
use ieee.std_logic_1164.all;

entity hb1 is
port(
d : in std_logic_vector(8 downto 1);
q : out std_logic_vector(8 downto 1));
end hb1;

architecture behav of hb1 is
begin
process(d)
begin
case d is
when "11111110"=>q<="00000110";
when "11111101"=>q<="01011011";
when "11111011"=>q<="01001111";
when "11110111"=>q<="01100110";
when "11101111"=>q<="01101101";
when "11011111"=>q<="01111101";
when "10111111"=>q<="00000111";
when "01111111"=>q<="01111111";
when others=>q<="00000000";
end case;
end process;
end behav;