qiangdaqi8.rpt

几个VHDL实现的源程序及其代码

-- Equation name is '_LC5_C3', type is buried 
-- synthesized logic cell 
_LC5_C3  = LCELL( _EQ026);
  _EQ026 = !_LC3_C6 &  _LC5_C11 & !_LC6_C6;

-- Node name is '|HB1:37|:406' 
-- Equation name is '_LC8_C3', type is buried 
_LC8_C3  = LCELL( _EQ027);
  _EQ027 =  _LC5_C3 & !_LC5_C6 &  _LC6_C3 & !_LC7_C6;

-- Node name is '|HB1:37|:438' 
-- Equation name is '_LC6_C4', type is buried 
_LC6_C4  = LCELL( _EQ028);
  _EQ028 =  _LC4_C3 & !_LC8_C3
         #  _LC3_C3 & !_LC8_C3
         #  _LC5_C4 & !_LC8_C3;

-- Node name is '|HB1:37|:454' 
-- Equation name is '_LC5_C4', type is buried 
!_LC5_C4 = _LC5_C4~NOT;
_LC5_C4~NOT = LCELL( _EQ029);
  _EQ029 = !_LC3_C11 & !_LC4_C6
         # !_LC3_C11 &  _LC4_C1;

-- Node name is '|HB1:37|:465' 
-- Equation name is '_LC4_C4', type is buried 
!_LC4_C4 = _LC4_C4~NOT;
_LC4_C4~NOT = LCELL( _EQ030);
  _EQ030 = !_LC5_C4
         #  _LC4_C3
         #  _LC3_C3
         #  _LC8_C3;

-- Node name is '|HB1:37|:475' 
-- Equation name is '_LC8_C11', type is buried 
!_LC8_C11 = _LC8_C11~NOT;
_LC8_C11~NOT = LCELL( _EQ031);
  _EQ031 = !_LC2_C11 & !_LC3_C6
         #  _LC2_C3 & !_LC2_C11
         # !_LC2_C11 & !_LC7_C11;

-- Node name is '|HB1:37|~489~1' 
-- Equation name is '_LC1_C11', type is buried 
-- synthesized logic cell 
_LC1_C11 = LCELL( _EQ032);
  _EQ032 =  _LC2_C6 & !_LC4_C6 & !_LC4_C11
         # !_LC2_C6 &  _LC4_C6 & !_LC4_C11
         # !_LC8_C11;

-- Node name is '|HB1:37|:492' 
-- Equation name is '_LC2_C4', type is buried 
!_LC2_C4 = _LC2_C4~NOT;
_LC2_C4~NOT = LCELL( _EQ033);
  _EQ033 =  _LC1_C11 & !_LC3_C3
         # !_LC3_C3 &  _LC4_C3
         #  _LC8_C3;

-- Node name is '|HB1:37|:505' 
-- Equation name is '_LC3_C11', type is buried 
!_LC3_C11 = _LC3_C11~NOT;
_LC3_C11~NOT = LCELL( _EQ034);
  _EQ034 = !_LC2_C6 & !_LC8_C11
         #  _LC4_C11 & !_LC8_C11
         #  _LC4_C6 & !_LC8_C11;

-- Node name is '|HB1:37|:513' 
-- Equation name is '_LC2_C2', type is buried 
!_LC2_C2 = _LC2_C2~NOT;
_LC2_C2~NOT = LCELL( _EQ035);
  _EQ035 = !_LC4_C1 &  _LC4_C6
         # !_LC3_C11;

-- Node name is '|HB1:37|:519' 
-- Equation name is '_LC1_C4', type is buried 
!_LC1_C4 = _LC1_C4~NOT;
_LC1_C4~NOT = LCELL( _EQ036);
  _EQ036 = !_LC2_C2 & !_LC3_C3 & !_LC4_C3
         #  _LC8_C3;

-- Node name is '|HB1:37|:532' 
-- Equation name is '_LC6_C1', type is buried 
!_LC6_C1 = _LC6_C1~NOT;
_LC6_C1~NOT = LCELL( _EQ037);
  _EQ037 = !_LC3_C11 &  _LC5_C1
         # !_LC3_C11 & !_LC6_C6
         # !_LC3_C11 & !_LC5_C11;

-- Node name is '|HB1:37|:535' 
-- Equation name is '_LC1_C1', type is buried 
_LC1_C1  = LCELL( _EQ038);
  _EQ038 = !_LC4_C1 &  _LC4_C6
         #  _LC6_C1;

-- Node name is '|HB1:37|:544' 
-- Equation name is '_LC7_C4', type is buried 
_LC7_C4  = LCELL( _EQ039);
  _EQ039 =  _LC1_C1 & !_LC3_C3
         # !_LC3_C3 &  _LC4_C3
         #  _LC8_C3;

-- Node name is '|HB1:37|:553' 
-- Equation name is '_LC7_C1', type is buried 
_LC7_C1  = LCELL( _EQ040);
  _EQ040 = !_LC2_C3 &  _LC3_C6 &  _LC5_C11 & !_LC6_C6
         # !_LC2_C3 & !_LC3_C6 &  _LC5_C11 &  _LC6_C6;

-- Node name is '|HB1:37|:562' 
-- Equation name is '_LC2_C1', type is buried 
_LC2_C1  = LCELL( _EQ041);
  _EQ041 = !_LC4_C1 &  _LC4_C6
         # !_LC2_C11 &  _LC8_C1;

-- Node name is '|HB1:37|~564~1' 
-- Equation name is '_LC8_C1', type is buried 
-- synthesized logic cell 
_LC8_C1  = LCELL( _EQ042);
  _EQ042 = !_LC2_C6 &  _LC7_C1
         #  _LC4_C11 &  _LC7_C1
         #  _LC4_C6 &  _LC7_C1;

-- Node name is '|HB1:37|:571' 
-- Equation name is '_LC8_C4', type is buried 
_LC8_C4  = LCELL( _EQ043);
  _EQ043 =  _LC2_C1
         #  _LC4_C3
         #  _LC3_C3
         #  _LC8_C3;

-- Node name is '|HB1:37|:594' 
-- Equation name is '_LC3_C1', type is buried 
!_LC3_C1 = _LC3_C1~NOT;
_LC3_C1~NOT = LCELL( _EQ044);
  _EQ044 = !_LC6_C1
         # !_LC4_C1 &  _LC4_C6;

-- Node name is '|HB1:37|:600' 
-- Equation name is '_LC3_C4', type is buried 
!_LC3_C4 = _LC3_C4~NOT;
_LC3_C4~NOT = LCELL( _EQ045);
  _EQ045 = !_LC3_C1 & !_LC3_C3 & !_LC4_C3
         #  _LC8_C3;

-- Node name is ':8' 
-- Equation name is '_LC6_C3', type is buried 
_LC6_C3  = DFFE( k1,  _LC1_C2,  CTL,  VCC,  VCC);

-- Node name is ':10' 
-- Equation name is '_LC5_C6', type is buried 
_LC5_C6  = DFFE( k2,  _LC1_C2,  CTL,  VCC,  VCC);

-- Node name is ':11' 
-- Equation name is '_LC4_C6', type is buried 
_LC4_C6  = DFFE( k4,  _LC1_C2,  CTL,  VCC,  VCC);

-- Node name is ':12' 
-- Equation name is '_LC7_C6', type is buried 
_LC7_C6  = DFFE( k3,  _LC1_C2,  CTL,  VCC,  VCC);

-- Node name is ':13' 
-- Equation name is '_LC3_C6', type is buried 
_LC3_C6  = DFFE( k8,  _LC1_C2,  CTL,  VCC,  VCC);

-- Node name is ':14' 
-- Equation name is '_LC6_C6', type is buried 
_LC6_C6  = DFFE( k7,  _LC1_C2,  CTL,  VCC,  VCC);

-- Node name is ':15' 
-- Equation name is '_LC1_C6', type is buried 
_LC1_C6  = DFFE( k6,  _LC1_C2,  CTL,  VCC,  VCC);

-- Node name is ':16' 
-- Equation name is '_LC2_C6', type is buried 
_LC2_C6  = DFFE( K5,  _LC1_C2,  CTL,  VCC,  VCC);

-- Node name is '~95~1' 
-- Equation name is '~95~1', location is LC1_C8, type is buried.
-- synthesized logic cell 
_LC1_C8  = LCELL( _EQ046);
  _EQ046 = !k1 & !k2 & !k3;

-- Node name is '~95~2' 
-- Equation name is '~95~2', location is LC8_C6, type is buried.
-- synthesized logic cell 
_LC8_C6  = LCELL( _EQ047);
  _EQ047 =  _LC1_C8 & !_LC2_C3 & !_LC4_C6 & !_LC6_C6;

-- Node name is '~95~3' 
-- Equation name is '~95~3', location is LC6_C7, type is buried.
-- synthesized logic cell 
_LC6_C7  = LCELL( _EQ048);
  _EQ048 = !_LC2_C6 &  _LC3_C4 &  _LC4_C7
         #  _LC2_C6 &  _LC5_C7;

-- Node name is '~95~4' 
-- Equation name is '~95~4', location is LC3_C7, type is buried.
-- synthesized logic cell 
_LC3_C7  = LCELL( _EQ049);
  _EQ049 = !k6 & !_LC1_C6 &  _LC6_C7
         #  k6 &  _LC8_C7;

-- Node name is '~95~5' 
-- Equation name is '~95~5', location is LC2_C12, type is buried.
-- synthesized logic cell 
_LC2_C12 = LCELL( _EQ050);
  _EQ050 =  _LC3_C7 &  _LC4_C4 &  _LC6_C4 &  _LC8_C6;

-- Node name is '~95~6' 
-- Equation name is '~95~6', location is LC2_C8, type is buried.
-- synthesized logic cell 
_LC2_C8  = LCELL( _EQ051);
  _EQ051 = !k3 &  _LC5_C8 &  _LC8_C4
         # !k3 &  _LC7_C8;

-- Node name is '~95~7' 
-- Equation name is '~95~7', location is LC2_C7, type is buried.
-- synthesized logic cell 
_LC2_C7  = LCELL( _EQ052);
  _EQ052 = !K5 & !k6 & !k8;

-- Node name is '~95~8' 
-- Equation name is '~95~8', location is LC3_C12, type is buried.
-- synthesized logic cell 
_LC3_C12 = LCELL( _EQ053);
  _EQ053 =  _LC2_C7 &  _LC2_C8 & !_LC4_C4
         #  _LC2_C7 &  _LC3_C8 & !_LC4_C4;

-- Node name is '~95~9' 
-- Equation name is '~95~9', location is LC4_C12, type is buried.
-- synthesized logic cell 
_LC4_C12 = LCELL( _EQ054);
  _EQ054 = !k4 & !k7 &  _LC2_C12
         # !k4 & !k7 &  _LC3_C12;

-- Node name is '~95~10' 
-- Equation name is '~95~10', location is LC1_C3, type is buried.
-- synthesized logic cell 
_LC1_C3  = LCELL( _EQ055);
  _EQ055 = !_LC4_C1 &  _LC4_C6
         #  _LC1_C7 &  _LC7_C3;

-- Node name is '~95~11' 
-- Equation name is '~95~11', location is LC5_C12, type is buried.
-- synthesized logic cell 
_LC5_C12 = LCELL( _EQ056);
  _EQ056 =  _LC1_C3 &  _LC1_C8 &  _LC2_C7;

-- Node name is '~95~12' 
-- Equation name is '~95~12', location is LC8_C12, type is buried.
-- synthesized logic cell 
_LC8_C12 = LCELL( _EQ057);
  _EQ057 =  k7 &  _LC6_C12
         #  k4 & !k7 &  _LC7_C12;

-- Node name is ':95' 
-- Equation name is '_LC1_C12', type is buried 
_LC1_C12 = LCELL( _EQ058);
  _EQ058 =  clkspd &  _LC4_C12
         #  clkspd &  _LC5_C12 &  _LC8_C12;



Project Information                   d:\edaplay\digital\test18\qiangdaqi8.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 14,397K