📄 qiangdaqi8.rpt
字号:
- 7 - C 01 OR2 0 4 0 1 |HB1:37|:553
- 2 - C 01 OR2 0 4 0 1 |HB1:37|:562
- 8 - C 01 OR2 s 0 4 0 1 |HB1:37|~564~1
- 8 - C 04 OR2 0 4 1 1 |HB1:37|:571
- 3 - C 01 OR2 ! 0 3 0 1 |HB1:37|:594
- 3 - C 04 OR2 ! 0 4 1 3 |HB1:37|:600
- 6 - C 03 DFFE 2 1 0 5 :8
- 5 - C 06 DFFE 2 1 0 7 :10
- 4 - C 06 DFFE 2 1 0 14 :11
- 7 - C 06 DFFE 2 1 0 7 :12
- 3 - C 06 DFFE 2 1 0 8 :13
- 6 - C 06 DFFE 2 1 0 8 :14
- 1 - C 06 DFFE 2 1 0 6 :15
- 2 - C 06 DFFE 2 1 0 8 :16
- 1 - C 08 AND2 s 3 0 0 2 ~95~1
- 8 - C 06 AND2 s 0 4 0 1 ~95~2
- 6 - C 07 OR2 s 0 4 0 1 ~95~3
- 3 - C 07 OR2 s 1 3 0 1 ~95~4
- 2 - C 12 AND2 s 0 4 0 1 ~95~5
- 2 - C 08 OR2 s 1 3 0 1 ~95~6
- 2 - C 07 AND2 s 3 0 0 2 ~95~7
- 3 - C 12 OR2 s 0 4 0 1 ~95~8
- 4 - C 12 OR2 s 2 2 0 1 ~95~9
- 1 - C 03 OR2 s 0 4 0 1 ~95~10
- 5 - C 12 AND2 s 0 3 0 1 ~95~11
- 8 - C 12 OR2 s 2 2 0 1 ~95~12
- 1 - C 12 OR2 1 3 1 0 :95
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\edaplay\digital\test18\qiangdaqi8.rpt
qiangdaqi8
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 3/ 48( 6%) 0/ 48( 0%) 1/16( 6%) 4/16( 25%) 0/16( 0%)
B: 2/ 96( 2%) 4/ 48( 8%) 0/ 48( 0%) 2/16( 12%) 5/16( 31%) 0/16( 0%)
C: 18/ 96( 18%) 29/ 48( 60%) 0/ 48( 0%) 5/16( 31%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 6/24( 25%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\edaplay\digital\test18\qiangdaqi8.rpt
qiangdaqi8
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 8 |AND9:52|OUT
Device-Specific Information: d:\edaplay\digital\test18\qiangdaqi8.rpt
qiangdaqi8
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 CTL
Device-Specific Information: d:\edaplay\digital\test18\qiangdaqi8.rpt
qiangdaqi8
** EQUATIONS **
CLK : INPUT;
clkspd : INPUT;
CTL : INPUT;
k1 : INPUT;
k2 : INPUT;
k3 : INPUT;
k4 : INPUT;
K5 : INPUT;
k6 : INPUT;
k7 : INPUT;
k8 : INPUT;
-- Node name is 'clkspd~1'
-- Equation name is 'clkspd~1', location is LC4_C7, type is buried.
-- synthesized logic cell
_LC4_C7 = LCELL( _EQ001);
_EQ001 = !K5 & k8 & _LC3_C6;
-- Node name is 'clkspd~2'
-- Equation name is 'clkspd~2', location is LC5_C7, type is buried.
-- synthesized logic cell
_LC5_C7 = LCELL( _EQ002);
_EQ002 = K5 & !k8 & !_LC3_C6;
-- Node name is 'clkspd~3'
-- Equation name is 'clkspd~3', location is LC7_C7, type is buried.
-- synthesized logic cell
_LC7_C7 = LCELL( _EQ003);
_EQ003 = !_LC2_C6 & !_LC3_C6;
-- Node name is 'clkspd~4'
-- Equation name is 'clkspd~4', location is LC8_C7, type is buried.
-- synthesized logic cell
_LC8_C7 = LCELL( _EQ004);
_EQ004 = !K5 & !k8 & _LC1_C6 & _LC7_C7;
-- Node name is 'clkspd~5'
-- Equation name is 'clkspd~5', location is LC4_C8, type is buried.
-- synthesized logic cell
_LC4_C8 = LCELL( _EQ005);
_EQ005 = k1 & !k2 & !_LC2_C4 & !_LC6_C4;
-- Node name is 'clkspd~6'
-- Equation name is 'clkspd~6', location is LC5_C8, type is buried.
-- synthesized logic cell
_LC5_C8 = LCELL( _EQ006);
_EQ006 = !_LC1_C4 & !_LC3_C4 & _LC4_C8 & _LC7_C4;
-- Node name is 'clkspd~7'
-- Equation name is 'clkspd~7', location is LC1_C7, type is buried.
-- synthesized logic cell
_LC1_C7 = LCELL( _EQ007);
_EQ007 = !_LC1_C6 & !_LC4_C6 & !_LC6_C3 & _LC7_C7;
-- Node name is 'clkspd~8'
-- Equation name is 'clkspd~8', location is LC6_C8, type is buried.
-- synthesized logic cell
_LC6_C8 = LCELL( _EQ008);
_EQ008 = !k1 & _LC1_C7 & _LC6_C4 & !_LC6_C6;
-- Node name is 'clkspd~9'
-- Equation name is 'clkspd~9', location is LC7_C8, type is buried.
-- synthesized logic cell
_LC7_C8 = LCELL( _EQ009);
_EQ009 = k2 & _LC5_C6 & _LC6_C8 & !_LC7_C6;
-- Node name is 'clkspd~10'
-- Equation name is 'clkspd~10', location is LC8_C8, type is buried.
-- synthesized logic cell
_LC8_C8 = LCELL( _EQ010);
_EQ010 = !k2 & k3 & _LC7_C6;
-- Node name is 'clkspd~11'
-- Equation name is 'clkspd~11', location is LC3_C8, type is buried.
-- synthesized logic cell
_LC3_C8 = LCELL( _EQ011);
_EQ011 = !_LC5_C6 & _LC6_C8 & _LC8_C8;
-- Node name is 'clkspd~12'
-- Equation name is 'clkspd~12', location is LC7_C3, type is buried.
-- synthesized logic cell
_LC7_C3 = LCELL( _EQ012);
_EQ012 = k7 & !_LC5_C6 & _LC6_C6 & !_LC7_C6;
-- Node name is 'clkspd~13'
-- Equation name is 'clkspd~13', location is LC6_C12, type is buried.
-- synthesized logic cell
_LC6_C12 = LCELL( _EQ013);
_EQ013 = !k4 & _LC3_C4 & !_LC4_C4 & !_LC6_C4;
-- Node name is 'clkspd~14'
-- Equation name is 'clkspd~14', location is LC7_C12, type is buried.
-- synthesized logic cell
_LC7_C12 = LCELL( _EQ014);
_EQ014 = _LC4_C4 & _LC6_C4;
-- Node name is 'Q1'
-- Equation name is 'Q1', type is output
Q1 = _LC3_C4;
-- Node name is 'Q2'
-- Equation name is 'Q2', type is output
Q2 = _LC8_C4;
-- Node name is 'Q3'
-- Equation name is 'Q3', type is output
Q3 = _LC7_C4;
-- Node name is 'Q4'
-- Equation name is 'Q4', type is output
Q4 = _LC1_C4;
-- Node name is 'Q5'
-- Equation name is 'Q5', type is output
Q5 = _LC2_C4;
-- Node name is 'Q6'
-- Equation name is 'Q6', type is output
Q6 = _LC4_C4;
-- Node name is 'Q7'
-- Equation name is 'Q7', type is output
Q7 = _LC6_C4;
-- Node name is 'Q8'
-- Equation name is 'Q8', type is output
Q8 = GND;
-- Node name is 'SPEAK'
-- Equation name is 'SPEAK', type is output
SPEAK = _LC1_C12;
-- Node name is 'Y0'
-- Equation name is 'Y0', type is output
Y0 = GND;
-- Node name is 'Y1'
-- Equation name is 'Y1', type is output
Y1 = GND;
-- Node name is 'Y2'
-- Equation name is 'Y2', type is output
Y2 = GND;
-- Node name is 'Y3'
-- Equation name is 'Y3', type is output
Y3 = GND;
-- Node name is 'Y4'
-- Equation name is 'Y4', type is output
Y4 = GND;
-- Node name is 'Y5'
-- Equation name is 'Y5', type is output
Y5 = GND;
-- Node name is 'Y6'
-- Equation name is 'Y6', type is output
Y6 = GND;
-- Node name is 'Y7'
-- Equation name is 'Y7', type is output
Y7 = GND;
-- Node name is '|AND9:52|:2' = '|AND9:52|OUT'
-- Equation name is '_LC1_C2', type is buried
_LC1_C2 = LCELL( _EQ015);
_EQ015 = CLK & !_LC4_C1 & !_LC4_C6;
-- Node name is '|HB1:37|:306'
-- Equation name is '_LC2_C11', type is buried
!_LC2_C11 = _LC2_C11~NOT;
_LC2_C11~NOT = LCELL( _EQ016);
_EQ016 = _LC4_C6
# _LC2_C6
# _LC6_C11
# !_LC1_C6;
-- Node name is '|HB1:37|~346~1'
-- Equation name is '_LC2_C3', type is buried
-- synthesized logic cell
!_LC2_C3 = _LC2_C3~NOT;
_LC2_C3~NOT = LCELL( _EQ017);
_EQ017 = !_LC5_C6 & !_LC6_C3 & !_LC7_C6;
-- Node name is '|HB1:37|~346~2'
-- Equation name is '_LC6_C11', type is buried
-- synthesized logic cell
!_LC6_C11 = _LC6_C11~NOT;
_LC6_C11~NOT = LCELL( _EQ018);
_EQ018 = !_LC2_C3 & !_LC3_C6 & !_LC6_C6;
-- Node name is '|HB1:37|~346~3'
-- Equation name is '_LC4_C11', type is buried
-- synthesized logic cell
!_LC4_C11 = _LC4_C11~NOT;
_LC4_C11~NOT = LCELL( _EQ019);
_EQ019 = !_LC1_C6 & !_LC6_C11;
-- Node name is '|HB1:37|~346~4'
-- Equation name is '_LC4_C1', type is buried
-- synthesized logic cell
!_LC4_C1 = _LC4_C1~NOT;
_LC4_C1~NOT = LCELL( _EQ020);
_EQ020 = !_LC2_C6 & !_LC4_C11;
-- Node name is '|HB1:37|~346~5'
-- Equation name is '_LC5_C1', type is buried
-- synthesized logic cell
_LC5_C1 = LCELL( _EQ021);
_EQ021 = _LC3_C6
# _LC2_C3;
-- Node name is '|HB1:37|:366'
-- Equation name is '_LC4_C3', type is buried
!_LC4_C3 = _LC4_C3~NOT;
_LC4_C3~NOT = LCELL( _EQ022);
_EQ022 = _LC6_C3
# _LC5_C6
# !_LC5_C3
# !_LC7_C6;
-- Node name is '|HB1:37|:386'
-- Equation name is '_LC3_C3', type is buried
!_LC3_C3 = _LC3_C3~NOT;
_LC3_C3~NOT = LCELL( _EQ023);
_EQ023 = !_LC5_C3
# _LC7_C6
# !_LC5_C6
# _LC6_C3;
-- Node name is '|HB1:37|~406~1'
-- Equation name is '_LC5_C11', type is buried
-- synthesized logic cell
_LC5_C11 = LCELL( _EQ024);
_EQ024 = !_LC1_C6 & !_LC2_C6 & !_LC4_C6;
-- Node name is '|HB1:37|~406~2'
-- Equation name is '_LC7_C11', type is buried
-- synthesized logic cell
!_LC7_C11 = _LC7_C11~NOT;
_LC7_C11~NOT = LCELL( _EQ025);
_EQ025 = !_LC5_C11
# _LC6_C6;
-- Node name is '|HB1:37|~406~3'
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